Hi everyone,
I am using SignalTap to monitor the runtime-signals of my verilog design. However, I just have the situation, that after compiling the whole design in Quartus and when I want to add signals to SignalTap setup for monitoring, that using the SignalTap: pre-synthesis filter for some weird reasons some registers are enlisted, but some are not?!
Can some please explain why?
The registers, which are not listed in the NodeFinder, are used in the Verilog entity, i.e. they get written and read, so the reason for not being listed cannot be redundancy.
I hope you guys can help me out.
Many thanks,
Jimmy
I am using SignalTap to monitor the runtime-signals of my verilog design. However, I just have the situation, that after compiling the whole design in Quartus and when I want to add signals to SignalTap setup for monitoring, that using the SignalTap: pre-synthesis filter for some weird reasons some registers are enlisted, but some are not?!
Can some please explain why?
The registers, which are not listed in the NodeFinder, are used in the Verilog entity, i.e. they get written and read, so the reason for not being listed cannot be redundancy.
I hope you guys can help me out.
Many thanks,
Jimmy