VHDL syntax error ---- parser stack overf

Hallo

I am trying to use the FIR Interpolation Block from Simulink with 4096 coefficients and 256 upsampling. I using the hdl coder to generate the VHDL code and then Altera Quatrus 2 to synthesize the code. My HDL code generates perfectly. But when i try to synthesize it i run in to the following error

VHDL syntax error at FIR_Interpolation.vhd(11060) near text "2495"parser stack overflow FIR_Interpolation.vhd Line: 11060

I am attaching the VHDL file that i am generating.

Is it like i have too many filter coefficients? I am able to synthesize the filter with 512 coefficients set and 32 bit upsample. Then i tried the same filter with this setting and i get this error. Can anyone help me with the error?

Attached Files

• VHDL Code.zip (86.2 KB)