The .sof file seems to be download to cyclone ii successfully, but actually not
Hi, I used the quartus ii 11.1 to generate the .sof file, and downloaded to the cyclone ii. The tool Programer show "successfully". But when i tried to download nios to fpga flash in nios ii eclipse,...
View ArticleMatrix math example
Does anyone have a DSP builder file that shows an efficient way to do various matrix operations? My matrices are as small as 3x3 and as large as 10x10, and I will need to do matrix multiplications and...
View ArticleAvalon-MM PCIe Hard IP problem in 64bits address range
I'm using a Avalon-MM Hard IP for PCIe with a modular Scatter-Gather DMA (mSGDMA) on a Cyclone V. The FPGA PCIe is connected to a Window 10 CPU board. The Windows 10 driver I wrote is reading and...
View ArticleAltera EMAC Hwlib for Cyclone V SOC
Hi, I need to use Cyclone V HPS's EMAC interface without using linux OS. However, although the "alt_emac.h" is included in the Hardware Library for Cyclone V, I could find any source file relating to...
View ArticleWhat does "charge pump" and "loop filter components" do in Altera PLL?
What is the application of the "charge pump" and "loop filter components" and why should we want to be able to control them?
View Articlealt_irq_disable_all() not allowed in isr
Hello, Simple and general newbie question. I have inherited someones code which uses HAL irq legacy functions. I noticed from the API reference that alt_irq_disable_all() is not allowed to be called...
View ArticleAbout altera Cyclone V package library
I need an altera Cyclone V package library,but i do not have.i want to download from altera website,but i didn't find it.who can give me an altera Cyclone V package library or tell me how to download...
View ArticleArria 10 External Memory Interface Pin Infromation
Hi, I am using MT41K256M16HA-125 IT:E DDR3 Interface with 10AS016E4F29ISG SoC. I had downloaded external memory interface information pin information file and pin out file. I need some clarifications...
View ArticleRequest of feedback on SPI Slave moduel
Hello I'm new on the hardware design world so probably I'm making a some beginner mistake. I need to write a SPI Slave module, my first attempt was to make a SPI slave module using as reference the...
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VHDL syntax error ---- parser stack overf
Hallo I am trying to use the FIR Interpolation Block from Simulink with 4096 coefficients and 256 upsampling. I using the hdl coder to generate the VHDL code and then Altera Quatrus 2 to synthesize the...
View ArticleStarting up with DEO-Nano-SoC board
hi I'm using the board DEO-Nano-SoC kit and I'm trying to install the OpenCL tools on the board. After reading the manuals "Altera SDK OpenCL - Getting Started Guide", "Altera RTE for OpenCLGetting...
View Articlequartus_map.exe crashed while elaborating design written with SystemVerilog
The stack dumping message is: Code: Problem Details Error: Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/verilog/verimisc_elab.cpp, Line: 460 type Stack Trace: 0x51b90:...
View ArticleBest Quartus II version for Cyclone V GX
I need to use Cyclone V GX, and I want to be sure of which is the most convinient version of Quartus for this family. I also pretend to use Cyclone III. Thanks.
View ArticleUsing the ADC IP core
Hi, I'm using the ADC IP core for the first time in my design on MAX10. I have initiated the IP core in the Qsys and selected the core variant as ADC core control only and have set all the parameters....
View Articlecommunication with a processor imx7
Hi everyone, I don't know if some of yours have already communicate the FPGA max 10 with the processor imx7 I need some explantation about, how FPGA could receive an information from processor and how...
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Can't place all Ram Cells in the design Issue
Hi, In my design I'm facing a weird problem. I have a ADC IP core in my design and whenever I'm enabling the debug path for the ADC the analysis and the synthesis of the design passes the test...
View ArticleCan't get a license for Quartue Prime 16.0
I just installed Quartus prime 16.0. I was using Quartus II 14.0. The company I work for bought several of the Cyclone V demo cards. We only used a couple of the licenses. You get a one year license...
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Counter, synthesize problems
Hi, I have problems with my counter. Sorry for my poor english Register should be reset on the posedge of signal x1 and should be increased on every posedge of CLOCK. I know that register and ENABLE...
View ArticleQuartus 16.0.0 no pof generated
I'm compiling code for a Cyclone IV using Quartus 16.0.0 and am finding that the pof file is not automatically generated during compilation. I get an sof, which I can convert to a pof using the...
View ArticleFPGA Cyclone V power from single DC/DC chip
I want to ask about the best power circuit for powering a Cyclone V chip. I don't mean a specific chip number, but I am concerned about how to generate all the supplies required. For all last designs I...
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