Install Tools without DS5
I'm attempting to use an Ubuntu 14.04 virtual private server to build the kernel, distro, and bootloader. When I try to install the 16.0 EDS I get an error because it is looking for xterm or a...
View ArticleFFT in DE0 Nano board
Hi, i have recently bough DE0 nano board and i am beginner in Verilog. I went through the ADC code given in CD and i am comfortable in understanding how the external data is captured using the ADC via...
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Avalon Streaming Interface Packages: EOP
Hello, I'm using Avalon Streaming Interface in Qsys to connect my components and Altera IPs. In my testbench, I read a file and use a data format adapter in order to put 4 symbols per clock cycle in...
View ArticleWhich files are necessary to back up for running timequest without compiling
would like to back up the result of FPGA(Altera) compilation, in order to be able to analyze the timing of a FPGA compilation, long time after compiling it. In addition I would like to reduce the size...
View ArticleCan't determine definition of operator ""srl""
Hallo This is my first project with Altera. I am using the quatras 2 synthesis tool and simulink to generate a design for my FPGA. But when i try to synthesis the code i get the following error can't...
View ArticleNeed to Flush L2 cache on Cyclone V even though disabled ?
I've been trying to turn on the L1 data cache during the decompression of my OS and struggling to get it working. I found that even though I could boot into the resulting OS image, 'random' 32-byte...
View ArticlePowerPlay Early Estimator Import Problem
I am using the PowerPlay Early Estimator for Cyclone II. I am trying to import a file generated by Quartus II 13.0sp1 (64-bit). The file is generated with 3 warnings, 0 errors. When PowerPlay Early...
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EPM240T100C5 not work reading data from RAM
Hi can someone help my with my code please module dds_generator(clk,signal_output);input wire clk;output wire [7:0] signal_output;reg [31:0] phase_acumulator;initial phase_acumulator = 32'd0;//assign...
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EPM240T100C5 not work reading data from RAM
Hi can someone help me with reading data from RAM, please my code is very easy look: Code: Code: module dds_generator(clk,signal_output); input wire clk; output wire [7:0] signal_output; reg [31:0]...
View ArticleGPIO high impetance
Hello everyone, I'm using an altera max 10 Does anyone know how I could put GPIO1.IO3 as input with internal pull-up thank you in advance
View ArticleIP upgrade fail
Hi, I have a design using several simple IPs (sqrt, muladd , rams etc) made on Altera Quartus 16. When i open the project with Quartus 15 it prompts for IP upgrade which fails in all but one IPs. Is...
View Articleclock delay
Hi everyone, I'm asking how can I produce a time delay for exemple, I want to put a pin to the ground, then 1s later, I wanna put the second pin to the ground I was exemple of program like after or...
View Articlenios II is processor or controller
Hi any one explain me nios II is processor or controller ?
View ArticleIs it possible to receive runt ethernet packets with Cyclone V HPS MACs ?
I have a switch core that sends management packets which are less than 64 bytes (the total frame is 22 bytes not counting preamble or FCS). I'm not finding options to allow this through. I think I can...
View Articlehow do i speed up place&route timing in cyclone V
Hi, I need help to find a way to speed up fitter time because it takes me over 4 hrs to done the fitter. my sdc file is not complicated and only 76% of usage for device resource. I don't know why what...
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Getting an error on Ubuntu while installation of Quartus prime Pro 16.0
I am using ubuntu 14.04 LTS 64 bit os. I tried to install Quartus prime pro 16.0 by running .sh(dev1_setup_pro) file, But I got error message as "You dont have Quartus Prime software installed in...
View ArticleI2C 'functions' with LEDs, not with PMODA port
I'd like to use the I2C interface so I used the 'I2C Master'in Qsys. I route the SCL and SDA outputs of the core to two GPIO pins of the PMODA connector of my Max 10 Development Kit board. This does...
View ArticleDE1-SOC Cortex A9 Hard FPU
Hi, I am trying to compile a bare metal application on Eclipse DS-5 which takes advantage of the FPU engines in the Cortex A9 processor with the Cyclone V SoC. I set the compiler and assembler options...
View ArticleWhy is the use of different PLL feedback modes in Altera devices?
The documentation states that the Altera PLLs have 6 different clock feedback modes. These are: 1. Direct mode 2. Normal mode 3. Source-Synchronous mode 4. External Feedback mode 5. Zero-Delay Buffer...
View ArticleDo fPLL must be calibration with USRCLK even though used as a core PLL
Hi , How to use fPLL with core mode for Arria10? We don't need transceiver in our design, just need fPLL for fractional clock output. BUT USRCLK used as a general purpose IO is not feeded by a free...
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