Hi can someone help me with reading data from RAM, please
my code is very easy look:
compile project without errors but not use any CPLD resources :confused:
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RTL viewer : I thinks this is good
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I dont know why :(
thaks for help me
my code is very easy look:
Code:
Code:
module dds_generator(clk,signal_output);
input wire clk;
output wire [7:0] signal_output;
reg [31:0] phase_acumulator;
initial phase_acumulator = 32'd0;
//assign signal_output = phase_acumulator[31:31-7];
ram1_port sin(
.address(phase_acumulator[31:31-7]),
.data(),
.outclock(clk),
.we(1'b0),
.q(signal_output));
always@( posedge clk ) begin
phase_acumulator <= phase_acumulator + 32'd85899; //
end
endmodulecompile project without errors but not use any CPLD resources :confused:
RTL viewer : I thinks this is good
I dont know why :(
thaks for help me