Hi can someone help my with my code please
module dds_generator(clk,signal_output);input wire clk;output wire [7:0] signal_output;reg [31:0] phase_acumulator;initial phase_acumulator = 32'd0;//assign signal_output = ~phase_acumulator[31:24]; ram_1port sin( .address(phase_acumulator[31:24]), .data(), .outclock(clk), .we(1'b0), .q(signal_output));always@(posedge clk ) begin phase_acumulator <= phase_acumulator + 32'd85899346;end endmodule
This code is compiling but not use any CPLD resource, I dont know why
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RTL viewer
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RAM1_port
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And sorry but my english is not good :) , Thanks very much for helping me
module dds_generator(clk,signal_output);input wire clk;output wire [7:0] signal_output;reg [31:0] phase_acumulator;initial phase_acumulator = 32'd0;//assign signal_output = ~phase_acumulator[31:24]; ram_1port sin( .address(phase_acumulator[31:24]), .data(), .outclock(clk), .we(1'b0), .q(signal_output));always@(posedge clk ) begin phase_acumulator <= phase_acumulator + 32'd85899346;end endmodule
This code is compiling but not use any CPLD resource, I dont know why
RTL viewer
RAM1_port
And sorry but my english is not good :) , Thanks very much for helping me