I'm trying to use a VQM netlist generated by Synplify in Quartus. The netlist is intended to specify a VHDL sub-component <my_block> (not the FPGA top-level), and is included in my tcl flow with the following command (along with all of my VHDL source files):
set_global_assignment -name VQM_FILE <file>.vqm
I get the following error when I try to compile in Quartus:
Error (10481): VHDL Use Clause error at <file>.vhd(<line>): design library "<library>" does not contain primary unit "<my_block>". Verify that the primary unit exists in the library and has been successfully compiled.
Never having tried this before, it isn't obvious to me how to tell Quartus to look at the VQM file for the definition of <my_block> in <my_library>.
Has anyone tried this?
set_global_assignment -name VQM_FILE <file>.vqm
I get the following error when I try to compile in Quartus:
Error (10481): VHDL Use Clause error at <file>.vhd(<line>): design library "<library>" does not contain primary unit "<my_block>". Verify that the primary unit exists in the library and has been successfully compiled.
Never having tried this before, it isn't obvious to me how to tell Quartus to look at the VQM file for the definition of <my_block> in <my_library>.
Has anyone tried this?