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fft in Altera fixed point vs block floating point
Hello! I'm modeling two variants of Altera's fft (FFT IP Core) in Matlab, one - for block floating point and second - for fixed point. As a result I see block floating point heavily depends on level of...
View ArticleCheck resource info using Quartus command-line
Hi gurus, Is there any way to check the resource info (eg like LABCELL, FF, or DSP and etc ..) for each coordinate in chip planner using command-line (tcl console) ? I mean not to open chip planner and...
View ArticleHow to use a module or interface instance in an interface?
Hello,every one! I have some problem in using interface of SystemVerilog: I have a predefined module and interface, and I want to use them in another interface. The example code of module in interface...
View ArticleLVDS in Stratix iv
Hi, I'm working on a project with a pair of high speed LVDS ports. The FPGA board that I'm using is DE4 which is using a stratix IV EP4SGX530 as the FPGA. How can I check if the LVDS is working? The...
View ArticleError (12077): Node instance "Mult0" instantiated with unknown parameter...
I am using version 13.1 of Quartus II and this error keeps coming up. There is no where in my code that I can find this node instance or parameter. I did a bit of research to see if other people had...
View ArticlePin Assignements Wont Display in BDF Schematic File after compilation
Please Help.. For the life of me I cannot get I/O pin assignments to appear on my BDF file. I realize the question is vague, but I am stuck. Using QUARTUS II Software with MAX II 1270T144 device. I...
View ArticleIP Core configuration file
Greetings! I am trying to find a better solution to a file sharing system for our firmware developing team. Currently we are sharing the source code (.vhd, .v files), projet files (.qpf and .qsf), plus...
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Arria V hold time violations
I am getting some hold time violations reported in my ArriaV design and I am trying to make sense of the TimeQuest report. The violations are buried down in a VIP IP block in my Qsys subsystem. When I...
View ArticleSchematic for " PCI Express Development Kit, Stratix II GX Edition"?
Anyone have the schematic for the Stratix II GX kit shown here: https://www.altera.com/products/boar...ress_s2gx.html I have found everything else online (BOM, User Guide, Ref Manual) aside from the...
View ArticleDMA's Front and Back Buffer Address Translator
Hi Friends, I want to use the "DMA's Front and Back Buffer Address Translator " IP core, but i can't find the description of the register map of it. Does anyone have imformation about this? Any help...
View Article16x2 lcd interface from 8 bits to 4 bits in the hal driver
Hi everyone, I am trying to use the altera_avalon_lcd_16207 Driver to drive my Lcd and its working fine for me. But when I am trying to work with 4 bits interface using the same altera_avalon_lcd_16207...
View ArticleBlack Box and SIMULINK Model
Hallo Everyone For my project we need an I2S interface to get audio input. I got some existing VHDL code for an I2S receiver which i can use. I modeling my algorithm in Simulink and then using the HDL...
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storing ADC data to SDRAM
Hello. First of all, I am really sorry about my poor english and grammer that irritates you. I'm going to make my own system which's gathering 14-bit analog signal through ADC and Storing them to...
View Article30-day evaluation license with Quartus Prime Lite 16.0 ??
On August 10 I installed Quartus Prime Lite Edition 16.0. Since then I ran a few University Program Tutorials on a DE1-SoC board successfully. On August 30, upon starting Quartus I got the following...
View Articlereset sync design logic
I have a question regarding reset sync logic . first of all what I understood about requirement of reset synchronization in design : - Reset will be asynchronous in nature. - It is not an issue if...
View ArticleQuartus not recognizing VHDL functions in 2008 version of ieee.numeric_std
I have a bunch of VHDL code that works in SynplifyPro, but I'm having trouble getting it working in Quartus. It appears that Quartus is using an outdated version of ieee.numeric_std, but I have no idea...
View Articledts .compatibility for pata_platform.c
Thanks in advance. I'm using the Altera MAX0 evaluation board with the ghrd design PLUS added an IDE interface on the HSMC connector (it has a compact flash). I am now using the current Linux-socfpg...
View ArticleMAX10m08 board SDRAM access example
Hi, I'm a student and new to FPGA design. I'm trying to access external SDRAM on MAX10M09 board via SDRAM controller. The main idea is to write into a certain address with a certain value and then read...
View ArticleIssues with Max10 push button
Hi, I'm using MAX10 FPGA development kit with 10M50D F484 package FPGA. But I'm having some problems regarding using the push buttons present in the board. As per the data sheet the push button has to...
View ArticleUsing a VQM netlist file
I'm trying to use a VQM netlist generated by Synplify in Quartus. The netlist is intended to specify a VHDL sub-component <my_block> (not the FPGA top-level), and is included in my tcl flow with...
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