Msim transcript error while simulating testbench
Hi, I am trying to simulate a test bench through RTL simulation from Quartus II (15.0). I get the following error: 'Error deleting msim transcript permission denied'. Could anyone help to fix this...
View ArticleСannot get .sof and .pof files
Hello. I use Quartus Standard 9.0 However, when I compile a project I cannot get .sof and .pof files I get a message "Warning: Can't generate programming files for project because design file...
View ArticleNIOS II & Eclipse: Unresolved Inclusion Error
Hi! I'm using NIOS II SBT. When i attemt to build project which uses libraries "system.h", "alt_types.h" or "io.h" it gives me "Unresolved inclusion system.h" error. Code from Altera's uart example....
View ArticleHow to buy 1 or 2 Cyclone V GT FPGAs for protype board?
Hi, I have a need for 1-2 pieces of the below Cyclone V GT FPGA for a prototype board. I can not find any distributors that carry them. It is possible to buy 1-2 units from Altera as samples? I can not...
View ArticleUnable to simulate the testbench in Modesim
Hi, I have program for an OR gate which I am able to compile successfully in Quartus II. I am trying to simulate the design in Modelsim using RTL simulation. When Modesim opens up only the OR gate...
View ArticleHow can i get the frame rate by the frame count in the CCD capture
Excuse me , i want to know how to get the frame rate Frame count means the all frame you have got in the time? but i don't know the time value i use signal taps to get the frame count value , i am not...
View ArticleReplace PLL settings with new one
Simple Q, I hope - I'm just starting out with Altera & Quartus. I've successfully added an ALTPLL from the IP Catalog to my project (Quartus Prime 16.0 Lite, Linux). Now I'd like to re-synthesise...
View ArticleThe font size inside the block diagram symbols are to large?
When creating a schematic using the block diagram the font size inside the symbols are too large. I already tried going to options > and changed all font sizes to a smaller size. I have a windows 10...
View ArticleAbsolute maximum I/O/Analog pin input current
Hi, For the MAX10 family, what's the absolute maximum input current? Altera gives only the absolute maximum voltage (=4.12V). In my application I'm sampling with the MAX10 ADC an analog signal which...
View ArticleWant to Buy: Cyclone V GT FPGA Development Kit
If anyone has a used Cyclone V GT development kit no longer needed, I'd like purchase it. I can offer about half the new price. https://www.altera.com/products/boar...lone-v-gt.html Please PM me.
View ArticleInterposer card for ADS41B25 / MAX10
Hi Will this interposer card www.ti.com/tool/hsmc-adc-bridge connect this ADC board store.ti.com/ADS41B25EVM-ADS41B25-Evaluation-Module-P2541.aspx with this FPGA board...
View ArticleHelp needed in VHDL Testbench
Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the dir_s is...
View ArticleHow to debug the work item which global id is not 0? Using the emulator.
How to debug the work item which global id is not 0? Using the emulator. Using gdb to debug the host program and the kernels, I can break in the kernel code. But I can only debug the 0 work item. So I...
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PCIe link training fails, CV_DE1(rootport) CVGT (endpoint)
Hi All! I faced with the task to build a PCIe based system. For debugging a rootport part of the system I use Terasic DE1 Cyclone V GX based board equipped with special rootport<->hsmc (x1)...
View ArticleRemote hardware debugging through SLD Hub Controller IP
Hello, existing hardware debug examples are using "SLD Hub Controller System" IP to expose a MM interface to JTAG debug functions. It's internally translated to ST interface. Alternatively "SLD Hub...
View Article5 Gbps USB 3.0 PIPE interface via Cyclone V GT 6 Gbps transceivers?
I'm considering using a Cyclone V GT (that has 6 Gbps transceivers) to implement a USB 3.0 protocol analyzer. The idea is to split the upstream and down stream signals (externally) and input a copy of...
View Articleelf code many times not running,lie idle one Night or hours, maybe run OK
My design includes a 1.8V Mobile DDR (which seems to be working fine), a Serial Flash,Micron 256Mbit, UART. NIOS reset vector: epcs Controller , exception vector: DDR controller, the whole project be...
View ArticleHas anyone ever utilized opencl with opengl to be operated or executed upon...
Has anyone ever utilized opencl with opengl to be operated or executed upon an Altera FPGA supporting opencl ?? What has been the experience of people using altera FPGAS for graphics and or simulations...
View ArticleMAX 3000a Ioh and Iol specifications
Hello guys, Ioh and Iol are not specified for the MAX 3000a series in their databook. I needed to use it for power consumption estimation of Pdcout. Please, how can I go about this estimation without...
View ArticleLVDS output High Z or both to '0'
Hi, I have LVDS output. Is there a any way to put both LVDS outputs to High-'Z' or either both driving '0' ? -Tero
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