Hi all,
I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the dir_s is incremented only for one value ie. when fmcw_ramp_o >= fmcw_bw_i and for all other values its zero. Because of this, Ì am getting this error "wrong output: addition should take place". I don't know how to solve this problem.
I know for sure that dir_s should be 1 till it reaches the condition. I need to know how dir_s will be 1 continuously till fmcw_ramp_o< fstep_i or = "0000". The code looks like this:
Also the VHDL code looks like this:
I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the dir_s is incremented only for one value ie. when fmcw_ramp_o >= fmcw_bw_i and for all other values its zero. Because of this, Ì am getting this error "wrong output: addition should take place". I don't know how to solve this problem.
I know for sure that dir_s should be 1 till it reaches the condition. I need to know how dir_s will be 1 continuously till fmcw_ramp_o< fstep_i or = "0000". The code looks like this:
Code:
p_check_step: process(delayed_rst_s, clk_128meg_i)
begin
if (delayed_rst_s = '0') then
dir_s <= '0';
old_fmcw_ramp_s <= (others => '0');
elsif (clk_128meg_i'event and clk_128meg_i = '0') then
if (enable_i = '1' and fmcw_trig_i = '1') then
if( dir_s = '0') then
assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) + unsigned(fstep_i)) report " wrong output: addition should take place" severity error;
else
assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) - unsigned(fstep_i)) report " wrong output: subtraction should take place" severity error;
end if;
if (fmcw_ramp_o >= fmcw_bw_i) then
dir_s <= '1';
elsif (fmcw_ramp_o < fstep_i) then
dir_s <= '0';
elsif (fmcw_ramp_o = "000000000000000000000000") then
dir_s <= '0';
end if;
old_fmcw_ramp_s <= fmcw_ramp_o;
else
dir_s <= '0';
old_fmcw_ramp_s <= (others => '0');
end if;
end if;
end process;Code:
begin
if (reset_n_i = '0') then
temp_s <= 0;
cnt_s <= '0';
elsif (clk_128meg_i'event and clk_128meg_i = '1') then
if (enable_i = '1' and fmcw_trig_i = '1') then
if (temp_s <= to_integer(unsigned(fstep_i))) then
temp_s <= temp_s + to_integer(unsigned(fstep_i)); -- Accumulated values of temp_s and fstep_i
cnt_s <= '0';
elsif (temp_s = 0) then
temp_s <= temp_s - to_integer(unsigned(fstep_i));
cnt_s <= '0';
elsif (temp_s >= (to_integer(unsigned(fmcw_bw_i)))) then
temp_s <= temp_s - to_integer(unsigned(fstep_i));
cnt_s <= '1';
elsif (cnt_s = '0') then
temp_s <= temp_s + to_integer(unsigned(fstep_i)); -- Up counter
else
temp_s <= temp_s - to_integer(unsigned(fstep_i)); -- Down counter
end if;
else
temp_s <= 0;
cnt_s <= '0';
end if;
end if;
end process;