What's the Altera Equivalent to the Xilinx STARTUP Primitive GSR/GlobalSetReset?
Here's an example of what it looks like for Xilinx:
// Instantiating STARTUP symbol
STARTUP U1 (.GSR(global_reset));
always @(posedge clk or posedge global_reset) begin
if (global_reset) begin
dff <= 1'b0;
end
else begin
dff <= xyz;
end
end
Ok...Altera how to do it without needing a clock and initial conditions to create a global reset?
The reason why I ask is because I have a QSYS with an HPS core that is outputing a clock from a pll and the top-level FPGA doesn't have a Clock or reset pin that is accessable to the FPGA logic...
Here's an example of what it looks like for Xilinx:
// Instantiating STARTUP symbol
STARTUP U1 (.GSR(global_reset));
always @(posedge clk or posedge global_reset) begin
if (global_reset) begin
dff <= 1'b0;
end
else begin
dff <= xyz;
end
end
Ok...Altera how to do it without needing a clock and initial conditions to create a global reset?
The reason why I ask is because I have a QSYS with an HPS core that is outputing a clock from a pll and the top-level FPGA doesn't have a Clock or reset pin that is accessable to the FPGA logic...