hi, everyone,
I have a design using alt_pll Source Synchronous mode, and I make the data input pin "rx" an PLL Compensation assignment.
When builded with Quartus 9.1, the "rx" input register was placed in the fast io register as expected.
But when builded with Quartus 13.1, a warning showed
"Warning (15062): PLL "altpll0:inst|altpll:altpll_component|altpll_s6m2: auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register"
and the input register connected with "rx" was not placed in a fast io input register. TimeQuest report also have a 3ns skew.
why this happened?
thanks
JHH
I have a design using alt_pll Source Synchronous mode, and I make the data input pin "rx" an PLL Compensation assignment.
When builded with Quartus 9.1, the "rx" input register was placed in the fast io register as expected.
But when builded with Quartus 13.1, a warning showed
"Warning (15062): PLL "altpll0:inst|altpll:altpll_component|altpll_s6m2: auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register"
and the input register connected with "rx" was not placed in a fast io input register. TimeQuest report also have a 3ns skew.
why this happened?
thanks
JHH