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FPGA Counter Catch Eight game(error 10476, error 10558)
hi, im new to VHDL coding as im still learning the basics, i need to design a counter catch eight game and i have done the code but it shows and error and i am not able to solve it. it will be very...
View ArticleFunny Internal Error: Sub-system: VRFX
I found a funny bug in quartus_map. it crash when compiling the following module: Code: module crashtest(  input   clk,  input   rst ); reg loc_reset = 0; always @(posedge clk or posedge rst)...
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How to constrain a parallel bus from a PLL clock?
Hi. I have a couple of questions about the my design. Basically I have an FPGA which has a big data table which the values are readed and sent to an external DAC. The reading process and the DAC are...
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Simple problem with clock generation
Hi there, I am experiencing an apparently simple, but frustating problem: when I generate a clock signal with a process that shows an empty sensitivity list, modelsim simulation returns an undefined...
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Resetting the MAX10 to factory restore
Hi, I'm using MAX10 FPGA development kit with 10M50D F484 package FPGA. I'm trying to resetting the board to factory restore but while doing so it throws an error whose screenshot I have posted. Can...
View Articlehandling two dimensional array using vhdl
i have a two dimensional array in a text file. i want to read it from the text file and write it in another text file as a two dimensional array. i have tried using the code given below. but it writes...
View ArticleCyclone V deserializer maximum bitrate
Cyclone V datasheet states that the maximum data rate "Fhdsr" is 875 MBit/sec with SERDES factor "J" = 4 to 10. However, SERDES megafunction for Cycone V E device accepts 1GBit/sec at SERDES factor of...
View ArticleMAX 10 m 08 reset
Hi I'm using Altera MAX 10 10M08, in the guide user i found two push button resets, I'm looking for all registers reset (SW1) pin location but I can't found does any one has an idea. Thks all
View Articlehow do i view verilog parameters
Hi, In an elaborated design how can I see which parameters have been passed to each block in the hierarchy - ie overiding the default parameters in the module definition. Is there a way of seeing this...
View ArticleAll Pins list with tool Pin Planner
I use Quartus II 14.1 I canÂ’t see the window All Pins list with tool Pin Planner. Thank you for your help
View ArticleUse Monitor Program compiler Cortex- A9 program, prompt math library error
I use a tersic DE1 - SoC development board.Have joined in the program header file < math.h >,but when I use Monitor Program(v14.1) compiler architecture A9 program, the compiler shows the...
View Articleprogramming configuration flash with some data
I use external flash for configuration of FPGA. And I should use another external EEPROM for some data. However, If I use flash devce which have larger space than "bit file + ROM data". How can I...
View ArticleCyclone 5 pcie example project failure
Hi all, I'm new in altera world. My first board is cyclone 5 soc development board. I'm interested in pcie applications. From rocket board side, I found an example project but I couldn't compile it....
View ArticleHigh bandwidth data transfer between hps and fpga
Hi, I need to High bandwidth data transfer between hps and fpga. Which bridge should i use? I used light weight bridge but the speed of transfer data was up to 3MHz. Best Regards
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MCP2515 CANbus implementation in NIOS using alt_avalon_spi_command on 10M50DA
Hello, Straight off, I am a newbie to the FPGA game, but am (trying to) temporarily help fill a hole on our team. I have an Altera 10M50DA, and am attempting to implement CANbus communication using an...
View ArticleIt may sound naive.. Is there any good open source FPGA design? for education...
Hello I've been trying to learn some designing HW by FPGA verilog. My background is, I have experience about building customized PIO using DE1-SoC, hashing support HW,, and not much. I think it is...
View ArticleCFI timings Numonyx PC28F00AP30BFA
I have a custom board which is based on the FSM shared bus design. where a Cyclone 5 and Max 5 share a 16 bit data and 26 bit address bus and control signals. connected to this bus is a Numonyx...
View ArticleArria 10 Triple Speed Ethernet IP Core Settings
Hello All, I am attempting to use the Triple Speed Ethernet core on an Arria 10 GX development board but I am unsure what settings to use to make it work. I tired to use the RJ-45 connector on the...
View ArticleSource Synchronous mode in different quartus version
hi, everyone, I have a design using alt_pll Source Synchronous mode, and I make the data input pin "rx" an PLL Compensation assignment. When builded with Quartus 9.1, the "rx" input register was placed...
View ArticleNativeLink_simulation.rpt Error Report. How Can I correct the Error?
Hello all, I launched a testbench simulation using NativeLink and I got these errors reported in the ...nativelink_simulation.rpt file. Error: (vsim-SDF-3250)...
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