Meaning of "Design Instance Name" in EDA Netlist Writer Settings in Quartus II.
Hi all, What does "Design Instance Name" mean down at this link in the Quartus II? Assignments > Settings > EDA Tools Setting > Simulations > EDA Netlist Writer Settings. Thanks in advance....
View ArticleMy DE5-NET board have problem. aocl command doesn't work.
I buy DE5-net for opencl. My PC is composed epc612d8a-tb(mother board) and Xeon cpu e5-2630 v3. My operating system is centos 6.5 I follow OpenCL User Manual in terasic home page. aocl flash acl0...
View ArticleCannot compile .aocx files
I have the Altera Cyclone V SoC board and have installed OpenCL SDK 16.0.2.222 I am also dual booting Windows 10 and Ubuntu 16.04 and I have tried both OS's with different issues when I followed the...
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hexout versus jic delta in arria V epcs128
We are writing our flash device with the contents of the .hexout file (bit reversed across 8bit words). this is working fine on the arria 2 devices but not so well on the arria 5. We are bit banging on...
View ArticleVHDL- Quartus II (Web Edition) - size of the constante of std_logic_vector type
Hello Everybody, I would like using different constants of std_logic_vector type like that, because I want to using the numeric value : Code: constant VAL_MAX_COMPTEUR_2HZ : std_logic_vector(19...
View ArticleNetwork acquisition failing after web server implementation
i have implemented web server on our custom board using tse mac and standard web server code in nios. after running the code, the nios console displays upto web server starting up, but the network is...
View ArticleNeed help with understanding this VHDL assignment
Taking a course in VHDL and it seems very fun so far. However, I am stuck on trying to understand this assignment, it is about creating a 4-bit carry look ahead adder in VHDL but the adder should not...
View Article[HDL 9-806] Syntax error near "library IEEE".
I just started learning VHDL. The syntax I already have an my code is correct according to research I have done, but I keep getting this error that won't let me synthesis my code. I have pasted my code...
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[ De1-soc ] Helping me with a problem about HPS DMA example
This my error when i debug project ! ERROR(CMD16-TAD274-NAL33): # in E:\Altera-SoCFPGA-HardwareLib-DMA-CV-GNU\debug-hosted.ds:17 while executing: loadfile "u-boot-spl.axf" 0x0 ! Failed to load...
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max10 wrong pin number information on pdf
After developing my IP core and testing on a development board I built my board. I designed footprint and symbol on cad then I made the artwork, sent to manufacturing now board doesn't work. After...
View ArticleNo feasible entries for subprogram read
I don't understand: I have used this piece of code over and over again, it has always worked. Instead, now I can't get rid of the error No feasible entries for subprogram "read". Any idea would be of...
View ArticleMultiple windows opening in Modelsim Student version
Hii...I am using MODELSIM student edition 10.4a. Every time I am trying to open a .vhd file within the program from project window, multiple windows open... how do i fix it? I have tried to restart the...
View ArticleFSK Modulation in VHDL
Hello, I have written a testbench which performs FSK modulation. The testbench should perform the auto checks such that when fsk_data_i(0) = '1' then I need to push fsk_u_i to fsk_mod_o whereas if...
View ArticleEnable live I/O check
Helo Evrybody I use Quartus 14.1 View Live I/O check status window is greyed, disable. Accordingly Enable Live I/O check also. How do I activate that?
View ArticleSwapping RAM and registers
Hi, I'm synthesizing a large VHDL component and I'd like to swap some elements from memory to registers to compare the results. Is it possible/how? Thank you.
View ArticleQuartus II 14.0 compatibility issue with 13.0
Hi All, I have a question regarding compatibility issue. I have recently installed Quartus II 14.0 in my laptop. When I tried to use colleagues project file (.qar) to re-generate binary file (.sof),...
View ArticleNios talking with a my VHDL peripheral
I am trying to develop a system with my development kit which basically consists of: I provide my input data through the four pushbuttons to NiosNios, with this information, accesses - through simple...
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Issue with CIC filter implementation using DSP builder.
Hi, I'm implementing a 2 stage CIC decimation(/1000) filter using the DSP builder but not using the CIC block rather using adder and substractor to implement it. As per my calculation the CIC filter...
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Input pins never detect a LO
All, My setup: Quartus II 9.0 MAX-II schematic entry Don't know if this is a Quartus II issue or MAX-II issue. No matter what I set my pins to I can never detect a LO (GND) (simple circuit schematic)...
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