Need help with understanding this VHDL assignment

Taking a course in VHDL and it seems very fun so far.


However, I am stuck on trying to understand this assignment, it is about creating a 4-bit carry look ahead adder in VHDL but the adder should not have a generate or a propagate output. What does that mean? How am I supposed to create a carry look ahead without a generate or a propagate? I am interpreting this as I am supposed to replace generate with (A AND B) and propagate with (A XOR B). What do you guys think?


Thanks in advance :)