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Question Regarding to the MAX V eval board.
I am new user try to run my simple test on Altera Max V eval kit. I wrote a simple code want to verify a simple function: in file counter.v Code: module counter( CLOCK_10KHZ, counter_out, RESET); input...
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Max 10 Invalid internal configuration mode for design with memory init Q16.0
I started a new project in Quartus 16.0, I have a Qsys Nios II core with some peripherals attached. No matter what I do I get an error when I compile the processor with flash Error (14703): Invalid...
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NIOS II soft reset
Hi i am new to the NIOS II features. I am working on a cyclone V (5CEFA4U19C7) which has a Nios II processor in it. I want to do a soft reset which is, resetting the NIOS without power cycling it. I...
View ArticleI got this warning messages. Is is OK?
Hello, I don't have good english skills. but I want to know this mesaages as bellow. Warning (13012): Latch N_XDIO_OE_CPU$latch has unsafe behavior Warning (13013): Ports D and ENA on the latch are fed...
View ArticlePowerPlay estimation and asynchronous faster-than-clock signal: no clock...
Hi all, I am a newbie and I have a simple task at hand. I am working on a simple controller project on a Max3000A series device with an input signal that is faster than the system clock. This signal...
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Fitter I/O Rule Results in all pin
Hello I create another project and i canÂ’t find Fitter I/O Rules Results from customize columns for to add in All pin list. In my pervious project it exists. See the attached file Do you have a idea?...
View ArticleQuartus Prime not allowing apparently correct I/O assignment
Hi, I'm using Quartus Prime 15.1 and trying to program the DECA evaluation board. I've used a file provided by them to do the pin assignments. I am completely sure that I have used the correct one....
View ArticleVHDL problem
Hi everyone, I'm a new user of FPGA. I have 2 LEDs and a clock of 32KHz. So I wanna light up LED1 then light off LED 1 and light up LED2. Im trying to do something in VHDL, but it seems it's nonsense...
View ArticleMax10 On-Chip-Flash/Dual Configuration Unconstrained Clocks
Hi, I'm using altera_dual_boot and altera_onchip_flash in a MAX10M08DAF256C8G with Quartus Prime Lite 15.1.0. In TimeQuest I get the followed messages: Node:...
View ArticleHow to determine values of M, N, C, charge pump and loop filter for PLL...
The cyclone IV PLL takes in a 144 bit stream for PLL reconfig. This contains 18 bits for each C4, C3, C2, C1, C0, M and N and 9 bits each for charge pump and loop filter. This information is contained...
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DRAM problem U-Boot & customization
Hi everybody, I hope you're well. I've been working several days with meta-layer, because I'm working in a custom Altera SoCFPGA board trying to put linux, and I have two questions. Well my problem by...
View ArticleStratix 5 and PCIe Reference Design. How to change the target device ?
Hi everyone, I'm using a DE5-NET-450 development board from Terasic (http://www.terasic.com.tw/cgi-bin/pa...English&No=526) with a 5SGXEA7N2F45C2 FPGA and Quartus Prime 15.1.0. I'm trying to run...
View ArticleCyclone 5 PLLs
Is there a programatic way to re-configure the on chip PLLs? I don't mean loading a new .mif file, but rather having the embedded OS calculate the constants required to re-load the PLL for a different...
View Articleasmi_parallel mixed simulation
Trying to simulate the asmi_parallel IP in Modelsim. My code is VHDL, IP is Verilog. First attempt resulted in "Unresolved defparam reference to .." error occurring 13 times. Added altera_mf_ver and...
View ArticleMAX-II Input pins never detect a LO
All, I tried to post this in the Quartus II and Tools discussion but I have never received a response. My Setup: Quartus II 9.0 MAX-II PLD Schematic entry...
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Error 12006: undefined entity
Hi Everybody, I got this error Error (12006): Node instance "instrumentation_fabric" instantiates undefined entity "alt_sld_fab". Make sure that the required user library paths are specified correctly....
View Articleusing h2f_axi_master
Hi, I used h2f_lw_axi_master to transfer data between hps to fpga. in this state maximum rate to on/off one IO pin was 3MHz. to increase rate, I used h2f_axi_master. in this state the rate increased to...
View ArticleProblem with ALTCLKCTRL module and outputs from two different PLLs in Cyclone...
Hello! I'v got a Cyclone III device EP3C16U256. And i have got a two external clock signals 10 MHz and 30 MHz (they are connected to dedicated clock pins on different sides of FPGA). I want to make 120...
View ArticleUsing SPI and I2C on MAX10
Hi Community, I have a question about using SPI and I2C with the MAX10. There are no dedicated pins for SPI and I2C on the MAX10 pin description. Does that mean I can decide which pins I want to use...
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