Hello,
I have written a testbench which performs FSK modulation. The testbench should perform the auto checks such that when fsk_data_i(0) = '1' then I need to push fsk_u_i to fsk_mod_o whereas if fsk_data_i(0) = '0' then I need to push fsk_l_i to fsk_mod_o. But it is not doing so in my code. I don't know why. Also I am getting an error " Index 22 out of bound 21 downto 0". The tetbench code looks like this:
And the VHDL code is as follows:
I couldn't figure out what the mistake is. Can anyone help me out. Thanks in advance.
I have written a testbench which performs FSK modulation. The testbench should perform the auto checks such that when fsk_data_i(0) = '1' then I need to push fsk_u_i to fsk_mod_o whereas if fsk_data_i(0) = '0' then I need to push fsk_l_i to fsk_mod_o. But it is not doing so in my code. I don't know why. Also I am getting an error " Index 22 out of bound 21 downto 0". The tetbench code looks like this:
Code:
stim_proc: process
begin
wait for 10 ns;
reset_n_i <='1';
wait for clk_128meg_i_period;
enable_i <='1';
--fsk_u_i <= "10001000"; -- 136
--fsk_l_i <= "11101000"; -- 232
--fsk_data_i <= "1111000010101010111010"; -- 3943098
new_fsk_u_s <= "10101010";
new_fsk_l_s <= "11110000";
new_fsk_data_s <= "1110101101010101010111";
wait for 1 ns;
new_fsk_u_s <= "10001000";
new_fsk_l_s <= "11101000";
new_fsk_data_s <= "1111000010101010111010";
wait for 10 ms;
reset_n_i <= '0';
wait for 1 ms;
reset_n_i <= '1';
wait for 1 ms;
enable_i <= '0';
wait for 1 ms;
enable_i <= '1';
wait for 1 ms;
assert false report "End of simulation" severity failure;
end process;
delay_rst_s <= reset_n_i after 1 ns;
p_check :process(delay_rst_s, clk_128meg_i)
begin
if (delay_rst_s = '0') then
clk_cycles_s <= (others => '0');
cnt_s <= (others => '0');
assert fsk_mod_o = "00000000" report " Output is not set to default value when reset_n_i is 0" severity error;
elsif (clk_128meg_i'event and clk_128meg_i = '0') then
if (enable_i = '1') then
clk_cycles_s <= std_logic_vector(unsigned(clk_cycles_s) + 1);
if (clk_cycles_s >= "1111111111") then
cnt_s <= std_logic_vector(unsigned(cnt_s) + 1);
if(fsk_data_i(to_integer(unsigned(cnt_s))) = '1') then
assert fsk_mod_o = std_logic_vector(fsk_u_i) report " Wrong output: fsk_u_i should be shifted " severity error;
elsif (fsk_data_i(to_integer(unsigned(cnt_s))) = '0') then
assert fsk_mod_o = std_logic_vector(fsk_l_i) report " Wrong output: fsk_l_i should be shifted " severity error;
end if;
end if;
else
cnt_s <= (others =>'0');
clk_cycles_s <= (others => '0');
end if;
end if;
end process;Code:
begin
p_fsk_mod : process(reset_n_i, clk_128meg_i)
begin
if (reset_n_i = '0') then
temp_s <= (others => '0');
cnt_s <= (others => '0');
cntdiv_s <= (others => '0');
elsif (clk_128meg_i'event and clk_128meg_i = '1') then
if (enable_i = '1') then
cntdiv_s <= std_logic_vector(unsigned(cntdiv_s) + 1); -- counter to count the clock cycles--
if (cntdiv_s >= "1111111111") then -- condition to check if the clock cycle is equal to 1023--
cnt_s <= std_logic_vector(unsigned(cnt_s) + 1); -- increment the "logik" block--
if (fsk_data_i(to_integer((unsigned(cnt_s)))) = '1') then -- shift the bits of fsk_data_i according to the value of the "logik" block--
temp_s <= std_logic_vector(fsk_u_i); -- perform the muliplexer operation based on the bits being pushed by the "logik" block--
else
temp_s <= std_logic_vector(fsk_l_i);
end if;
end if;
else
temp_s <= (others => '0');
cnt_s <= (others => '0');
cntdiv_s <= (others => '0');
end if;
end if;
end process;
fsk_mod_o <= temp_s ;