DE1-SOC memory interface

I am trying to understand the memory interface between OpenCL generated code and the SDRAM. One thing that is puzzling me is the fact that the OpenCL interface is 256 bit wide (both in the board_env.xml as a channel, and in the generated code) whereas the bus itself is 32-bit wide (according to specs). Is there any specific reason why this is the best choice? Does the OpenCL mem interface generate a burst of 8 for every memory request, hence getting the 256-bit data. Also, i am assuming there are no caches on the FPGA side since the AXI is supposed to work with non-caching accelerators, so are the 256-bits stored to be possibly reused if a sequential access is required?

I am relatively new to Verilog, so might have missed something completely obvious in the verilog code.
Thanks,