"Definitive" Terasic DE1-SoC Device Tree
Is there a Terasic released device tree for this board?
View Articledigital watch
hello every one i have design digital watch second , minute , hour after i execute the code the counter second and minute counter ok work . for 0 to 59 but hour counter form 0 to 99 ? i have question...
View ArticleuCOS-II task profiler
I am currently using uCOS-II as the operating system in my Nios with the Altera provided Eclipse based development environment. I was wondering if there are any tools provided by Altera, plugins for...
View ArticleAltera De0 soc not support on 32-bit version
I'm currently using 32-bit PC. I also have De0-nano-soc, Cyclone5-5CSEMA4U23C6 board. There's no proper Quartus2 version support for 32-bit version. please give me a solution
View ArticleIs there a way to send periodic time updates to an FPGA over JTAG/UART?
Hi all, Would there be a way to periodically send NTP network time updates from my computer to a Nios II over JTAG/UART? I am aware that it is possible to install an embedded version of Linux (uCLinux)...
View ArticleDynamic reconfiguration of Arria 10 Transceiver PHY
I would like to dynamically reconfigure my Arria 10 Transceiver PHY. I use reset controller IP and reconfiguration interface for the purpose. From the user guide, I understand that the steps to perform...
View ArticleHow to "regenerate" an input clock if it's a burst clock
Hi guys, I have a Cyclone IV E and I have an external board which output a 27 Mhz clock with 8 bit data. The board at the end the chain needs to work another couple of signals (valid and sync) that I...
View ArticleProblems in getting the Triple Speed Ethernet core to work
Hello everyone, I am using a Cyclone V on a SoCKit board (link here) (provided by Terasic), connecting an HSMC-NET daughter card (link here) to it in order to create a system that can communicate using...
View ArticleProject Suggestions?
Hello everyone! I am wanting to reproduce an old 70's/80's BMC decoder circuit, composed of lots of 7400 logic gates. Some of these chips are quite obsolete now and using a CPLD or something of that...
View ArticleQuery FPGA device ID from Linux
We have a board that accepts both an Cyclone V SX or ST part, and also one with more or less logic. Given device availability varies considerably, we have some boards built with one part and some with...
View ArticleSimulation Report NOT RESPONDING
Working on a lab assignment for my class. I enter in my code and compile with no errors. Then I make a vector wave form (which my text says generate net list). I follow the directions step by step! I...
View Articletroubles with Windows 10
Hi, I'm trying to connect a DEO-Nano board under windows 10 OS, I have tried several versions of QUARTUS II to get the correct USB-blaster drivers, but without any success. I have even tried to load...
View Article32-bit Quartus Prime Standalone Programmer
Hello, I understand that Quartus hasn't been available for 32-bit since version 14 - but I am looking for the 32-bit version of the standalone programmer which appears to be a thing judging from this...
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DDR3 calibration fail (Cyclone V + Micron DDR3 + Uniphy + NiOS)
Dear All, help me please in a trouble. I have a custom board with CycloneV (including Hard-IP DDR) and DDR3 (MT41J128M16JT-125). In Quartus II v14.1.0 (64bit) I created SoC (NIOSII + block ram + hard...
View ArticleDE1-SOC memory interface
I am trying to understand the memory interface between OpenCL generated code and the SDRAM. One thing that is puzzling me is the fact that the OpenCL interface is 256 bit wide (both in the...
View Articlea calculator using altera monitor program
I am working on simple calculator on altera De2-70 board, using altera monitor program. i am continuously getting errors for syntax in c on altera monitor program. does it use different syntax or just...
View ArticleGetting Started With Stratix V DE5 5SGXEA7N2F45C2 FGPA
Hello, I'm a university student and my research lab was donated a DE5 Stratix V FGPA (5SGXEA7N2F45C2). However, it came with no data sheets, manuals, startup guides, etc (I had to guess what board we...
View ArticleCyclone 5 PLLs part II
Part I of my question involved being able to re-configure PLLs from Linux and that part is now working great. Part II - I'm trying to create a low jitter clock with a frequency range from 1000Hz to...
View ArticleSimulating a design, developed using OpenCL
Hi, I am totally a newbie on this, so pardon me if I ask any dumb questions. Suppose I design a simple adder using OpenCL then how I do simulate it. Like, may be I am not sure in my design that which...
View ArticleWarning: RST port on the PLL is not properly connected
Hello! I'm using PLL in my project for the Cyclone V device. And i have this warning in Quartus (Quartus Prime 16.0): Quote: Warning: RST port on the PLL is not properly connected on instance pll100:...
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