Hi,
I am totally a newbie on this, so pardon me if I ask any dumb questions.
Suppose I design a simple adder using OpenCL then how I do simulate it. Like, may be I am not sure in my design that which signal is getting asserted at what time. So is there any way I can simulate and observe the results before putting my design on FPGA ?
I am totally a newbie on this, so pardon me if I ask any dumb questions.
Suppose I design a simple adder using OpenCL then how I do simulate it. Like, may be I am not sure in my design that which signal is getting asserted at what time. So is there any way I can simulate and observe the results before putting my design on FPGA ?