Hi,
Can someone share experence about power saving in FPGA designs?
I am facing power consumption and heat disipation problems. I tried disabling clocks but that gives very litle diference in power consumption. What else could be done to reduce power consumption?
Can someone share experence about power saving in FPGA designs?
I am facing power consumption and heat disipation problems. I tried disabling clocks but that gives very litle diference in power consumption. What else could be done to reduce power consumption?