Error when verifying QSPI Flash
Hello - I am getting the message below intermittently during the verify of an FPGA (and spl at times) image. The FPGA does not load so there may be another problem too but I was wondering if anyone has...
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DMA Speed Issues
Hi all, I have a QSYS design with the basic DMA controller. I have found numerous issues with this DMA controller and have managed to work around most of the issues but stuck at one last one. Avalon to...
View ArticleAOC crashes when using kernel with function calls
Hi everyone, I am new to the Altera world and I am using the altera aoc compiler for implementing my OpenCL application on an Altera FPGA. I have a kernel code, written in OpenCL that calls some...
View ArticleUsing the Transceiver Toolkit
Hi, I am trying to use the transceiver toolkit to do BER testing and generate EyeQ diagrams. Do I need to generate a tcl script through ModelSim before using the transceiver toolkit? I tried jumping...
View ArticleQuestion about component and packag
Hello, I am new to VHDL. I have a question about using a component in the package body which is defined in package head. But there is error about the port map in the package body. Could anyone help me...
View ArticlestratixV GX development kit && display port
Recently ,I have studied the Stratix V GX development kit board with the display port daughter board. I downloaded the DisplayPort Design Example 13.0(TX Only)from the altera website. After compling,I...
View ArticleIORD 11.0 vs IORD 9.1
Hello, Code: Quote: int main() { int i; while(1) { i = IORD_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_BASE); printf("PIO EDGE CAP: %d\n", i); IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_BASE, 0x0); usleep(1000000);...
View ArticleQuartus Prime Lite OpenCL Licensing
The link below says that the OpenCL SDK is available on the free Quartus Prime Lite Edition, but that it requires an additional license: https://www.altera.com/content/dam/a...comparison.pdf How do I...
View ArticlePower saving techniques for FPGA
Hi, Can someone share experence about power saving in FPGA designs? I am facing power consumption and heat disipation problems. I tried disabling clocks but that gives very litle diference in power...
View ArticleOpenCL design without a host
I'm quite new to OpenCL. Is it possible to create an OpenCL kernel design without the need for a host ? watching the latest OpenCL tutorials for AOCL SDK 16.1 suggest kernels can now be started...
View ArticleVerify Failed using SDRAM on a DE0 following Altera's tutorial
Hi folks, I know this has come up countless times - I have read plenty of these threads over the past couple of days. Forewarning that I am very new to FPGA programming/development so I don't have a...
View ArticleMissing IP Cores in IP Catalog
Hi, I want to use some peripheral interface IP cores in my design, specifically the SPI and I2C master cores. They are there in the document labelled "Embedded Peripheral IP User Guide" but I can't...
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VGA - output of a graphic not stable
Hello Community, I got a problem with my current VGA project. Here a few informations about what I want to do: - first ten 8-bit-rows are used to display some text like variables or sth similar. -->...
View ArticleQuartus II 16 standard version Crashed problem. HELP!
When i compile my project, the quartus always crashed at 95% of Fitter(Replace & Route). Then the pop up window says the quartus meet unexpected error. the error code is following: "wildcard:***...
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How to merge two or more buses?
I'm sorry for asking what it is probably a silly question, but i'm having trouble trying to merge 3 buses(2 buses containing 5 bits(0..4), 1 bus containing 16 bits(0..15) into one bus containing 26...
View ArticlePLL outputs on 3.3V IO bank of CycloneIV
Hi : Is it allowed to configure pll clock outputs as differential mode when the bank IO voltage is 3.3V. If so, does VCCA provide the +2.5V for this kind of LVDS mode? Is it same as the banks assigned...
View ArticleDetect high impedance on the input pin
Hi to all, for my little project, I need to manage the output pin of any FPGA placing them at high impedance. This is not a problem, I can do it with MAX10 and Cyclone IV. However I would need to...
View ArticleMegaWizard 2x8k Dual Port Memory
Try to Convert a Project to Cyclone III but need Help with the Memory Type Orginal Code Code: module vidram( output [7:0] data_out, // cpu interface...
View ArticlePLL cascading on Cyclone V - broken?
I'm trying to cascade 2 plls on the Cyclone V (5CEBA2F23C8). Both integer. I set the first to have a cascade_out and the 2nd to have adjpllin. Then I connect these. Even with an otherwise empty project...
View ArticleQsys not generating same files in Simulation folder for VHDL vs Verilog?
So I have wondered what is going on here and it seems there is a bug in the program. I am using Altera Quartus II 15.0 64 bit. I select SRAM/SSRAM controller from the IP catalog. Then I click generate...
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