latency in 1 port ram help
Hello, I am new to vhdl. I am using the on chip RAM and the built in integer comparator to do something as following: 1. memory_a & memory_b both are the on chip ram with size 32 bit * 128 with...
View Articledid anyone have ever use the fpga to send the msi interrupt
did anyone have ever use the fpga to send the msi interrupt,why i read the Message Upper Address，Message Lower Address,Message Data register at first,they are all 0,and then i configure these register...
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Making a block diagram and I get the error "missing source signal"
I'm using Quartus Prime Lite Edition. The error I'm receiving is; Error (275044): Port "datab[3..0]" of type multiplier of instance "inst" is missing source signal I've checked my block diagram over...
View ArticleReading HIP PCIe Rootport Configuration Space
Hi! What is the way to read the Configuration Space of HIP PCIe Rootport Avalon-MM (Cyclone V GX) from application software? Thanks in advance!!!
View ArticleDesign works with NIOS II/e, not II/f
I have a design in whch I read ADC samples from PIO with a dual clock FIFO input and transport the output data with SGDMA to on-chip memory. It took me a few days of experimenting to discover that the...
View ArticleNeed help with Ethernet on DE2i-150
Hi, I'm a newbie on both vhdl and nios. I'm doing a project on designing a simple trajectory simulation and transfer the data to PC to display on a software I wrote. I got stuck at transferring data to...
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DE0-Nano PLL "non-dedicated routing"
Hi there, I'm having a bit of difficulty getting to the bottom of some warnings to do with the PLL I am using on a Cyclone IV. I'm using the DE0-Nano from Terasic. The 50MHZ onboard oscillator is...
View ArticleIs it possible to read or write data on every clk cycle in Avalon MM interface?
Provided that one is using a simple Avalon MM interface with waitrequest, is it possible to read or write data on every clock cycle or does one need to use avalon streaming interface or avalon mm burst...
View ArticleCyclone III LS Vccbat high current draw
Hi all, I developed board using EP3CLS70U484C8 with battery on it as supply for stored key. Battery is small about 85mAh and is connected to VCCBAT thru DS1314 chip. Everything works just fine except...
View ArticleSynchronization Register Chain?
I made a schematic and i've got multiple registers(32-bit store) created by myself. During the execution, i noticed that some values were not what i expected. It is giving me the result of some old...
View ArticleDevice Footprint Specs: MAX10 10M02V36
Hello, After searching the Altera website, I can't seem to find a document specifying the footprint for the MAX10 10M02V36 36-pin BGA. Does anyone know where I could locate this? The link provided here...
View Articlemax10 adc sample point
hi everyone: i try to use max10 on chip adc to sample a image sensor output. the frequence is 1MHz. i need to know when the max10 on chip adc switch from sample to the hold mode. in most adc, this is...
View ArticleWhat is the main purpose of having option for pipeline and latency in altera...
The arithmatic blocks found in the Altera IP suite e.g the LPM airthmatic blocks, have an option for pipelining and achieving latency for a specific number of clk cycles. What is the main purpose of...
View ArticleHow to square a fixed point number?
Assuming I have a 16 bit fixed point number that needs to be squared, how should this be implemented? The number format is Q2.14. Squaring it shall produce a result that is 32 bits instead and seems to...
View ArticleDoes Altera Quartus II contain an IP to calculate complex number magnitude?
I have fixed point complex numbers with 16 bit each for the real and imaginary parts, I shall be used Q2.14 format for each. Although I have found ALTMULT_COMPLEX which can multiply complex numbers and...
View ArticleAvalon MM slave register mapping in VHDL
Hi, I am a little bit confused on how the avalon memory mapping works. I hope someone can clarify this for me. I created a mm slave in VHDL. Which seems to work fine when accessed from the NIOS. At...
View ArticleConvert Programming Files tool and multiple Nios processors
Hi, I'm trying to create a *.pof file for programming that host 2 configurations and 2 Nios, one for each configuration. The problem seems to be that the "Convert Programming Files" tool from Quartus...
View ArticleHow important are System Design Contraint (*.sdc) files?
How important really is the SDC file? How important is it to eliminate all unconstrained paths? Does it have to be ALL of them? (such as altera_reserved_tdi and altera_reserved_tms that seem to work...
View Article30fps Output Frame Rate from Deinterlacer II?
I've been using the Deinterlacer II to deinterlace my 1080i60 video stream but I don't want the 1080p60 frame rate that it outputs. I see that the old Deinterlacer has the option to output a 1080p30...
View ArticleDownloading elf file failed on De2i-150
Hi, I'm a newbie. I'm having a problem using triple speed ethernet on De2i-150. I'm using the triple speed tutorial for De2-115, but I think they are quite similar. Apparently I'm having the same...
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