So I have wondered what is going on here and it seems there is a bug in the program. I am using Altera Quartus II 15.0 64 bit.
I select SRAM/SSRAM controller from the IP catalog. Then I click generate HDL and select Verilog for the "simulation" tab. Now I repeat the same process but select VHDL instead of verilog.
I notice that when I select VHDL I do not get a folder called "submodules" in the simulation folder. However, when I select Verilog, I do. The submodules folder is created and it contains a .v file containing source code for the SRAM/SSRAM controller. Why are different files being generated in the two cases? :confused:
This seems to be a bug in the program. :mad:
I select SRAM/SSRAM controller from the IP catalog. Then I click generate HDL and select Verilog for the "simulation" tab. Now I repeat the same process but select VHDL instead of verilog.
I notice that when I select VHDL I do not get a folder called "submodules" in the simulation folder. However, when I select Verilog, I do. The submodules folder is created and it contains a .v file containing source code for the SRAM/SSRAM controller. Why are different files being generated in the two cases? :confused:
This seems to be a bug in the program. :mad: