Setup:
Quartus II 12.1 Web
Cyclone IV GX transceiver starter board
I'm trying to do something which I thought would be relatively easy, but as been fighting me every step of the way and I would appreciate any and all help. Basically I want to be able to take custom logic in the form of verilog and use it to directly fiddle around in the qsys avalon MM realm. I've attached a project that is incredibly dumbed down (it won't do anything) for clarity but it presents what I'm trying to do if you don't want to read the following explanation.
Lets say I have some RAM in Qsys that I am interested in reading 1 32 bit word from. My previously designed logic is all contained in a top level .bdf so somehow I need to connect blocks and buses to qsys. I figured the best way to approach this is to first use the avalon MM interface spec info and recreate the timing shown there in a verilog file state machine using case statements because its extraordinarily easy to follow. Then using the component editor, load that in, show it the equivalent signal for each of the avalon specific signals, and then connect everything happily in qsys.
Now its not working because it gets hung up waiting for readValidData to be asserted which never happens. This to me means that something isn't getting through. I think the most likely scenario is somehow everything still isn't connected together. I put the verilog file in the synthesis bit, analyzed it, which generated the signals which I then told it were the appropriate avMM signals but it still seems upset (note: it compiles just fine, it just doesn't do anything)
now if anyone knows where in the world I'm going wrong (I am relatively certain I'm following the timing diagram with my state machine, it just doesn't seem to be asking for anything) OR anyone would care to explain to me how my actual project could/can be simulated I would be greatly appreciative. If I am going about this the complete wrong way too, I would be most appreciative but really the goal is just to see if I can communicate over the avalon MM fabric with verilog. RAM is just being used because I figured it was the simplest block to test on.
Many thanks!
sidenote: tried an avalon mm template too with little success and after several hours of battle and a frustrating lack of a timing diagram I gave up on that guy too
Quartus II 12.1 Web
Cyclone IV GX transceiver starter board
I'm trying to do something which I thought would be relatively easy, but as been fighting me every step of the way and I would appreciate any and all help. Basically I want to be able to take custom logic in the form of verilog and use it to directly fiddle around in the qsys avalon MM realm. I've attached a project that is incredibly dumbed down (it won't do anything) for clarity but it presents what I'm trying to do if you don't want to read the following explanation.
Lets say I have some RAM in Qsys that I am interested in reading 1 32 bit word from. My previously designed logic is all contained in a top level .bdf so somehow I need to connect blocks and buses to qsys. I figured the best way to approach this is to first use the avalon MM interface spec info and recreate the timing shown there in a verilog file state machine using case statements because its extraordinarily easy to follow. Then using the component editor, load that in, show it the equivalent signal for each of the avalon specific signals, and then connect everything happily in qsys.
Now its not working because it gets hung up waiting for readValidData to be asserted which never happens. This to me means that something isn't getting through. I think the most likely scenario is somehow everything still isn't connected together. I put the verilog file in the synthesis bit, analyzed it, which generated the signals which I then told it were the appropriate avMM signals but it still seems upset (note: it compiles just fine, it just doesn't do anything)
now if anyone knows where in the world I'm going wrong (I am relatively certain I'm following the timing diagram with my state machine, it just doesn't seem to be asking for anything) OR anyone would care to explain to me how my actual project could/can be simulated I would be greatly appreciative. If I am going about this the complete wrong way too, I would be most appreciative but really the goal is just to see if I can communicate over the avalon MM fabric with verilog. RAM is just being used because I figured it was the simplest block to test on.
Many thanks!
sidenote: tried an avalon mm template too with little success and after several hours of battle and a frustrating lack of a timing diagram I gave up on that guy too