ROM using altsyncram: timing question
Hi, Another newbie question. I have a simple ROM attached to my CPU, courtesy of altsyncram, and initialised using a .HEX file. All works, both in simulator and in the chip. My VHDL defaults the ROM...
View ArticleStratix V DSP Kit Transcievers
Hi, I was looking at the schematic and the reference manual for the Stratix V DSP development kit http://www.altera.com/products/devki...tix-v-dsp.html The transceivers are on Bank 1 of the HSMC ports...
View ArticleHELP with Verilog for a binary coded decimal converter
im trying to make a BCD converter with 5 input but there is something wrong with what I have here. please assist. module Lab08 (x, d); input [4:0] x; output [7:0] d; m0 = 5'b00000; m1 = 5'b00001; m2 =...
View ArticleDE5-NET JTAG Configuration Problem
Hi all, I tried to program the Stratix V FPGA on the DE5-NET board through the UBS Blaster cable. Each time, the programmer goes up to somewhere between 95% - 98% and fail. The error i get is "Error...
View ArticleTime analysis setting
Does the QuartusII Version 12.1 provide Time analysis settings (for example Enable multicorner timing analysis).? Because I didn't find this part in Setting tool.
View Articleit is not safe to use pixmap outside the gui thread
Hello I am new to linux i had try to install quartus 12.1 web edition using altera installer but after downloading while installing it shows the error "it is not safe to use pixmap outside the gui...
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Why i can't use CARRY&CARRY_SUM in QII11.1?
Hello Dears： I found i can use LCELL primitive in my project, but i can't use CARRY&CARRY_SUM primitive. My current QII version is 11.1+sp2. I remember i could use them in the old version. Also i...
View ArticleCyclone III configuration problem with Active Parallel flash
Hi, All, I've trying to store mt configuration and code data in an external flash, via Active Parallel interface. Using the Flash Programmer, I'm able to burn the .flash file to the external flash...
View ArticleCyclone 4GX DMA Controller - Read Address register truncation?
Hey everyone, I'm following Chapter 26 of the Embedded IP guide (DMA Controller). I've build a PCIE controller, DMA controller and onchip ram for a project I'm working on. My goal is to DMA from the...
View ArticleExperiments in look up, explore signals in FPGA
Hello, There's a problem in FPGA design is It's difficult to look up signal in FPGA design. If I can see signals in simulink very easily by taking a scope and lock at it. There's problem when I want to...
View Articlehierarchical QSYS and IRQ senders in a sub-block
Hi, I do my first steps with QSYS and I am building a NIOS II processor with on-chip RAM and some peripherals like SPI and PIO interfaces. I divided my design into 2 sub-designs; one sub-design has...
View ArticleProblem with IORD and IOWR instructions
Dear all, I have a qsys system composed of two NIOS that can access a shared memory (data masters are connected to the memory), when I use the instructions IORD and IOWR I don't obtain the right value...
View ArticleDE5-NET Not configuring
Hi all, I tried to program the Stratix V FPGA on the DE5-NET board through JTAG using the UBS Blaster cable. Each time, the programmer goes up to somewhere between 95% - 98% and fail. The error i get...
View ArticleHow to disable the following things in QuartusII
Hi, I am having trouble finding where to change the settings in QuartusII to achieve the following 2 things : 1. To disable the transformation of chains of registers into a shift-register primitive. 2....
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Qsys Component Editor for Custom Logic
Setup: Quartus II 12.1 Web Cyclone IV GX transceiver starter board I'm trying to do something which I thought would be relatively easy, but as been fighting me every step of the way and I would...
View Articlecannot execute quartus_sh in command line
Hi, Why I cannot run quartus_sh --flow compile top_level.v in my command prompt? the error message shown is 'quartus_sh' is not recognized as an internal or external command, operable program or batch...
View ArticleSet-up and hold time of ALTDDIO megafunction module
I am using the ALTDDIO megafunction in an Arria V device to capture incoming data of the order of 1Gbps and my timing simulation (using Time Quest Analyser) tells me that delays should be so adjusted...
View ArticlePCIe transmit and receive path latency
Hello everyone, I am trying to figure out how much latency for a certain configuration of the HIP PCIe MegaCore I can expect on both the transmitter and receiver path of an endpoint device. The reason...
View ArticleSily question: What is the maximum external clock for DE2 altera kit?
Can I try a very higher clock on DE2 board? Thank you, Tan
View ArticleCreate NiosII SBT (eclipse) project from cmake
Hi people, I am working on a rather big project (written in C), for which I am adding a Nios2 port. From the code-side, this is already done. Next step is to generate a NiosII SBT project from my...
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