Hello,
There's a problem in FPGA design is It's difficult to look up signal in FPGA design.
If I can see signals in simulink very easily by taking a scope and lock at it. There's problem when I want to explore signals in FPGA design. There's very few outputs, which I can connect to oscilloscope. I have to change output in code and re-compilate all design, which sometime take me 10 minuts.
What do you do in these case? Is there any tool can help me?
There's a problem in FPGA design is It's difficult to look up signal in FPGA design.
If I can see signals in simulink very easily by taking a scope and lock at it. There's problem when I want to explore signals in FPGA design. There's very few outputs, which I can connect to oscilloscope. I have to change output in code and re-compilate all design, which sometime take me 10 minuts.
What do you do in these case? Is there any tool can help me?