Hi! I am currently working with Cyclone V SoC and compilation time of my project is about 8 min long. My design includes HPS and some simple entities (7 segment driver for example). As I make some changes in mentioned entities I don't want to recompile my whole design. I have assigned partitions and selected post synthesis netlist, also I have selected option for forcing compiler to use post fitting netlist despite changes in the source code. Whatever I have tried with this options didn't gave me any time reduction in compilation time.
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