Greetings, I am wondering what the correct megafunctions/primitives are for implementing input/output dual-data-rate data lines for a DDR memory device. I'm on a Cyclone IV.
Here are my requirements:
1) Need to be able to tri-state the line to implement bi-directional
2) Need to output with dual-data rate, clocked from my internal clock
3) Need to input dual-data rate, clocked from the DDR's DQS (data strobe).
It seemed like the ALTDDIO_BIDIR was going to work, as it has an inclock, outclock, oe, and inclocken (can ignore DQS when in non-read states), but the simulation shows that I was only capturing input data on the rising edge of DQS...missing the data on the falling edge.
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What is the correct set of components to perform this?
Here are my requirements:
1) Need to be able to tri-state the line to implement bi-directional
2) Need to output with dual-data rate, clocked from my internal clock
3) Need to input dual-data rate, clocked from the DDR's DQS (data strobe).
It seemed like the ALTDDIO_BIDIR was going to work, as it has an inclock, outclock, oe, and inclocken (can ignore DQS when in non-read states), but the simulation shows that I was only capturing input data on the rising edge of DQS...missing the data on the falling edge.
What is the correct set of components to perform this?