Hi @ everyone!
In our project, lately we get a hold time violation.
FPGA: Cyclone V
Clk period: 31.625 ns
The signals where the violation occurs are intern signals.
In the attachment you can see more information.
How can I get rid of that violation?
In our project, lately we get a hold time violation.
FPGA: Cyclone V
Clk period: 31.625 ns
The signals where the violation occurs are intern signals.
In the attachment you can see more information.
How can I get rid of that violation?