Trying to solve a mystery, but after several days ran out of thoughts :(
Needed to connect to SignalTap around 100 (probably, a bit less) signals, and at some moment got very strange picture (attached):
First (upper) signal directly from PLL, 14.318 MHz frequency
Second signal inversion of first signal
SignalTap clock second output of the same PLL, 210MHz
The behavior of the circuit tells me that the signals are absolutely fine (nothing would work if the picture is true).
After removing most of signals to SignalTap (basically, keeping only the mentioned two signals), suddenly everything is OK no more strange glitches on the picture.
FPGA Cyclone IV, using DE2-115 board
Any thoughts would be greatly appreciated ! :)
Needed to connect to SignalTap around 100 (probably, a bit less) signals, and at some moment got very strange picture (attached):
First (upper) signal directly from PLL, 14.318 MHz frequency
Second signal inversion of first signal
SignalTap clock second output of the same PLL, 210MHz
The behavior of the circuit tells me that the signals are absolutely fine (nothing would work if the picture is true).
After removing most of signals to SignalTap (basically, keeping only the mentioned two signals), suddenly everything is OK no more strange glitches on the picture.
FPGA Cyclone IV, using DE2-115 board
Any thoughts would be greatly appreciated ! :)