Dear all hi;
I want to implement sigma delta ADC on FPGA (Altera DE1 cycloneII)
I used the code introduced by Lattice semiconductor (the document and the source code is attached) the codes were run on Quartus II successfully but when i checked the waveform on Modelsim the digital_out[7:0] is always 8'b0 and never changed i am new in verilog code and want to ask whether the problem derive from source code or testbench? and how can i fix it?
may sombody check the code please?
and also do these codes work on Altera DE cycloneII?
Thank you
I want to implement sigma delta ADC on FPGA (Altera DE1 cycloneII)
I used the code introduced by Lattice semiconductor (the document and the source code is attached) the codes were run on Quartus II successfully but when i checked the waveform on Modelsim the digital_out[7:0] is always 8'b0 and never changed i am new in verilog code and want to ask whether the problem derive from source code or testbench? and how can i fix it?
may sombody check the code please?
and also do these codes work on Altera DE cycloneII?
Thank you