Multiple FIR Megafunctions
Hi, I am trying to use multiple FIR filters on a Cyclone II. I current have 1 of 6 that compiles correctly. When I compile with all the .qip files include i get this error. Error (10430): VHDL Primary...
View ArticleError: (vcom-7)
Hiii i'm having same problem in this thead http://www.alteraforum.com/forum/showthread.php?t=26060 my case is that i'm used to compiling through gui not via cmd but whenever i select compile all or...
View ArticleAssign a part of a register for later use?
If I have a register like signal REG : signed (31 downto 0); and I will use every part of it for other purposes, it'll be a mess if I just take the whole part like REG (31 downto 24) <= ... REG (23)...
View ArticleNios II delay calculation
hi i am a beginner in nios ii. i just wanted to know how to create a delay of 5microseconds using c code for nios ii processor. i intend to assert particular values on PIO for specific time intervals...
View ArticleCustomize pattern generator created in Qsys
I did a design for Stratix V GX FPGA in order to transmit 3 independent channels. This design was created using qsys, also the pattern generator and the pattern_checker were created in qsys. Now I need...
View ArticleNewbie and Need assistance in using GPIO pins on DE2
Hello! I am new to using FPGA boards. I have experience with VHDL but not Verilog . I have a DE2 board and I would like if someone could direct me into the direction or assist in how I could use the...
View ArticleeCos interrupts (PIE in status register =0)
Hi all, my (timer) interrupt didn't work until I figured out, that bit 0 (PIE) in the status register is set to 0. So after all of my initialization stuff is done, I set that bit to 1. The system...
View ArticleCyclone IV PCIe Kit Reference Designs with PCI exoress test example
I have downloaded the PCIE reference design from the web: https://www.altera.com/support/softw...express-hp.jsp I have met several problems, First, altpcie_demo.exe looks for wdapi1021.dll, rather than...
View ArticleHelp for Simple Coding of 32Bit Fixed-Point Divider in Verilog
Sorry if this post might be repeating questions asked in earlier posts (most I checked didn't really help). I am using Verilog to program. My simple question is as following (it would be nice if the...
View ArticleWho can tell me the function of the chip EP4CS/EP6CS?
I am in the process of learning Quartus II tool. Any kind of help will be of great help to me. Thank you!
View ArticleStratix III - Quartus web edition 11.0
Hi, everyone My university has a XD2000i from xtremedata. XD2000 has a Stratix III EP3SE260F1152C3. On Altera's download page, I've found out that Quartus 11.0 web edition lists EP3SE260F1152C3 as a...
View ArticleTimeQuest : Report Timing on full path detail level but it shows only summary...
Hi, Just encountered with this problem right now. After I compiled the whole design, I run through TimeQuest and found certain violation. Hence I click on the those nodes, right click it and select...
View ArticleNios II Flash Programmer Errors!
So this isn't quite a C / C++ programming question, however I am attempting to run my web server (a slight modification of the demo web server) via the flash. I was able to get it running with the demo...
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NOR Flash Read write
hi all, in our project We are using Cyclone IV GX FPGA.We are using a NOR Flash(PC28F00BP30EF) connected to FPGA. We need to read and write data in to the NOR flash . I had attached the...
View Articledsp builder - multichannel duc
hello, i'm in need of timing diagram for a multichannel duc ( with valid and channel inputs). if anyone has implemented/used dsp builder, please post it regards nandakumar
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Could DSP Development Kit, Cyclone III Edition connect two Data conversion HSMC
Hi, I notice the DSP Development Kit, Cyclone III has two HSMC connector. Can I connect two Data conversion HSMC on it, left and right ? So that I can get 4 channels ADC. 未命名1.JPG Attached Images...
View ArticleQuartus GUI strangeness - changes shortcut key bindings
Ref: Quartus II 32-bit v12.1 Build 243 01/31/2013 SJ Web Edition Service Pack 1 Normally CTRL+L starts the compilation process. Occasionally the GUI seems to forget this and CTRL+L deletes a line of...
View ArticleHow to use open IP cores without the megawizard
I must have missed something, because I can't seem to find anything on how to use an IP core from for example opencores. I keep finding things about use the megawizard to generate IP cores, but I just...
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check the verilog code of ADC on FPGA
Dear all hi; I want to implement sigma delta ADC on FPGA (Altera DE1 cycloneII) I used the code introduced by Lattice semiconductor (the document and the source code is attached) the codes were run on...
View Article.sdc timing for opencores MAC v9.1
Hello I m integrating the opencores MAC 9.1 in our Cyclone IV device. For an application I use a simple socket server from the NIOS template. After some Ping commands (~100) I get errors on Frame...
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