Jtagd segfault on linux
Hi, I have Quartus 12.1sp1 setup and working with my hardware on Ubuntu 12.04 32-bit. However, the same configs on a 64-bit machine (which unfortunately I need to use) cause jtagd to segfault when...
View ArticleJust wiring two pins together
I'm sure this is a really easy answer, but I haven't been able to find it. Some signals were sent through my CPLD, someone thinking I might want to mess with them, and I don't for now, I just want to...
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SCFIFO megafunction not working!!
I have created a project by loading SCFIFO megafunction generated vhdl file. When I am simulating in MODELSIM, OUTPUT DATA is not coming even when the Read pulse is enabled. Someone kindly help....
View ArticleError: Can not generate netlist output
I'm trying to compile a program, I got this error when I get to final stage EDA netlist writter: Error: Can not generate netlist output files Because the license for encrypted file "C :/...
View ArticleError: Can not generate netlist output files
I'm trying to compile a program, I got this error when I get to final stage EDA netlist writter: Error: Can not generate netlist output files Because the license for encrypted file "C :/...
View ArticleConfiguring I2C bus in De1 board through nios
I have been working on a project we are facing a problem in configuring I2C bus for codec in de1 board and we dont know whether codec is in slave mode or master mode. I wanted to know how to configure...
View ArticleHow to generate simulation model for PCIe endpoint
Hi, I'm using Megawizard 12.1 to generate PCIe core. In previous versions, I remembered there were a checkbox for you to generate simulation model at the end of Megawizard core customization. That will...
View ArticleFailed to program flash
Hello everyone, Sorry about my poor english, i've developped a FPGA board which has a SST39VF6401B (Microchip flash), i'm using SOPC to configure the FPGA. I use Nios II to program flash (only blink...
View Articleimplementation of an arbitrary precision integer librar for usage in...
Hello, This requirement is a part of my thesis and I was wondering have anyone occurred to do a similar task of this sort. I plan to implement NIOS II custom instructions that will accelerate the speed...
View ArticleI2C Controller
Hey I really need help writing an I2C Controller that can perform a single byte write and a single byte read. Compensation may be given. Here is what I have so far: LIBRARY ieee;USE...
View Articlehow the data is transfered using PCIE LINK
I am using the altera S2GX for a project uses PCIE to transfer data. Now we have the hardware working with the PC, since altera didn't provide the source code for the pc app. I am not sure how the data...
View Articlehow the data is transfered using PCIE LINK
I am using the altera S2GX for a project uses PCIE to transfer data. Now we have the hardware working with the PC, since altera didn't provide the source code for the pc app. I am not sure how the data...
View ArticleAssigning pins in DE2 115
some one kindly help me in assigning pins for clock and the led for DE2 115 using quartus, Code: module FirstProject(clk, LED); output LED; input clk; reg [32:0] count1; reg LEDstatus;...
View ArticleBSP-Generation: Problem find custom device drivers from command line
Hello! I developed some own device drivers for some custom IPs. I added a _sw.tcl script to every device driver. Now I want to generate a bsp for a SOPC-Project from the command-line and the generation...
View ArticleLogic Analyzer Interface (LAI) destroys my design
Hi everyone! I have the following problem: I made a design with PCIe, I²C, SPI and a SRAM-Memory. The I²C- and SPI-Cores are made by myself and connected to the PCIe HIP with some PIOs. The SRAM is...
View ArticleWait statement error!!!
when i am using the following code clk_process: process begin clk<='0' wait for 10 ns;---ERROR COMING HERE clk<='1' wait for 10ns; end process ERROR IS : WAIT SHOULD COME WITH UNTIL CLAUSE......
View Articlerom generating code problem
hiii i've built my ROM containing data of 384000 i stated the data of 76800 and others to be "ZZ....ZZ" when i compile the code it takes time and finally return with this warning ( Warning:...
View Articlesignal spy in vhdl 2008
VHDL 2008 supports a direct hierarchical reference for signals. An example hierarchy is shown below. A <= <<signal top_ent.u_comp1.my_sig : std_logic_vector >>; Signal 'A' can be used to...
View ArticleDE3 cooling fan
Hi, I'm looking for a cooling fan for the Cyclone III chip on the Terasic DE3 board. Does anyone have any recommendations? I've been looking of the internet and can't any ones exactly for the board and...
View ArticleHelp with embedded fpga programming
Hi, im trying to program an acex chip via an embedded processor. im using a pic micro to program the acex via jtag. the ideas is have in an sd memory different configuration and load them as necessary....
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