signal spy in vhdl 2008

VHDL 2008 supports a direct hierarchical reference for signals. An example hierarchy is shown below.

A <= <<signal top_ent.u_comp1.my_sig : std_logic_vector >>;

Signal 'A' can be used to spy on signal 'my_sig' in u_comp1 which is instantiated inside top_ent using the above hierarchy.
However, there is a problem. modelsim is reporting error of 'unresolved reference to top_ent.u_comp1.my_sig' if the statement above is used inside a generate statement.
SpyGenofA : if instantiateablock = true generate
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A <= <<signal top_ent.u_comp1.my_sig : std_logic_vector >>;

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end generate;

However, if used outside a generate statement, it works fine.

Any idea what's going on....?