Quantcast
Channel: Altera Forums
Browsing all 19390 articles
Browse latest View live
↧

Quartus subscription edition - University

Hi, How one can get Quartus subscription edition 8.1 and 11.0 (linux if possible) for free by the altera's university program? Is it possible? What are the necessary steps? 1 - download the...

View Article


Image may be NSFW.
Clik here to view.

Flash Programmer error

When I program my flash memory i get an error "Resetting and Pausing Target Processor : FAILED".Is there any need to change my design? 6.JPG Attached Images 6.JPG (149.2 KB)

View Article


Image may be NSFW.
Clik here to view.

Implement Arduino into Altera FPGA

Hi, my name is Andy. I'm working on a 2m tall robot and try to use a FPGA to control it. I'm thinking to implement a Atmel softcore into my small Cyclone IV board. Did anyone try it before? Can the...

View Article

RAM and FLASH shared bus don't worked

Hello everyone, I developped my own custom board which have MT48LC16M16 (Micron SDRam), S29AL032D (Spansion Flash) and Cyclone III EP3C25. RAM and FLASH share data and address bus. The Flash memory is...

View Article

How to float I/O signals of EP910 devices

Hi, I work with a defense manufacturer who has qualified large number of EP910 devices. EP910 is currently not supported by Altera and not much information is available at altera.com Currently we are...

View Article


dsp builder-quartus project

hello, i have created a project for multichannel duc, and able to generate quartus project file. the top module is entity DUC is port ( Channel : in std_logic_vector(7 downto 0); Data : in...

View Article

xaui

how many transceiver channels are possible in xaui ip in altera stratix V? i am using it for 10GbE

View Article

error code: 8 for command

hi all, in my project am using CycloneIV EP4CGX74CF23I7, am trying to flash my External NOR Flash(PC28F00BP30EF) in Nios II Flash Programmer but am getting this error Info: Mar 28, 2013 12:52:59 PM -...

View Article


Malaysia Sales Representative for Altera

Hi, Who is Altera Representative in Malaysia? Do provide me their email address and contact number. Best regards -rudei-

View Article


CYCLON IV GX - ALTGX Won't recieve any valid data

Hello I'm new in the forum, seems like very nice one me and my partner working on a final project for the university engineering degree. We have designed and manufactured two printed circuits...

View Article

vhdl code for n*n matrix inversion

hello I want to write a vhdl code for real or complex matrix inversion. i don't know how i can send arrays of my matrix to output ports. i need your helps for writting this code because i'm beginner. tnx

View Article

multiple MSI in Qsys

Hello, I want to implement a design with multiple MSI interrupts. Until now I did it with Avalon ST (IP compiler for PCIe , MegaWizard). I tryied to implement it with avalon mm using Qsys but I faced...

View Article

Image may be NSFW.
Clik here to view.

DE1 Audio codec HELP !!!!! URGENT !!!!!

Hello, I'm a beginner and currently working on Altera DE1 board for Audio effects project. I want the audio codec to run in master mode for my project.The problem is that I am not able to configure the...

View Article


Altium schematic symbols (or Orcad 16.2 or earlier) for Cyclone V

I have tried downloading the Orcad symbols for cyclone V devices and converting them to Altium, but apparently the library format for Orcad changed at version 16.3 and the import tool does not...

View Article

Stratix III PLL Jitter Control

Hello, In my design using Stratix III FPGA, I have one dynamic reconfigurable PLL (top/bottom type). Beside setting up the parameters to generate output clocks [Fout = (Fin x M)/(N x C)], I would like...

View Article


Apical Image Sensor

I want to try Apical Image Sensor on Terasic DE2_115 board they have written "Your local Altera sales representative can assist you with the easy download of Apical's IP, registration for an evaluation...

View Article

Question regarding to PLL of Cyclone IV

There is a 40MHZ master clock in my system and I am using this master clock to generate a 160MHZ to capture the incoming data. The problem is sometimes I can capture the right data but sometimes I...

View Article


Drive leds with CPLD

Hello, sorry form my little question about currents. I'm trying to reduce the components usage of an board using a CPLD. I wan't to control buttons, leds and logic with a MAXV, but I'm not sure how...

View Article

Qsys project status indicates unsaved; even after I explicitly save (12.1)

My Qsys project appears to be unsaved even after I explicitly save via the file menu. I know this because 1) there is asterisks (*) beside the file name, which by convention indicates an unsaved file...

View Article

set_connection_parameter_value not callable from QSYS instance script?

Hello All, I would like to embed the SGDMA descriptor on-chip ram inside of a QSYS subsystem however for this to work properly the base address of the subsystem must be passed in so that the SGDMA...

View Article
Browsing all 19390 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>