dsp builder-quartus project

hello,

i have created a project for multichannel duc, and able to generate quartus project file.
the top module is

entity DUC is
port (
Channel : in std_logic_vector(7 downto 0);
Data : in std_logic_vector(15 downto 0);
Valid : in std_logic_vector(0 downto 0);
duc_i : out std_logic_vector(15 downto 0);
duc_q : out std_logic_vector(15 downto 0);
ochhannel : out std_logic_vector(7 downto 0);
ovalid : out std_logic_vector(0 downto 0);
busIn_d : in std_logic_vector(31 downto 0);
busIn_a : in std_logic_vector(15 downto 0);
busIn_w : in std_logic_vector(0 downto 0);
busOut_v : out std_logic_vector(0 downto 0);
busOut_r : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end;

can anyone tell me about those 3 signals...
what is the significant of those signals...
how do we provide those signals as input from outside?

regards
nandak