Hi all,
I am trying to synthesize a SystemVerilog (.sv) file in Quartus Prime Version 16.0.0.
I get the following error while using "for" statements without the explicit "generate" statement: (error) near text: "for"; expecting "endmodule"
The code snippet giving the error is as follows:
I get the above error in spite of having set the "Settings > Verilog HDL Input > Verilog version" to "SystemVerilog".
I have also included the comment "// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005" at the first line of my .sv file.
As a workaround, I can get Quartus to synthesize my file correctly using the following edited version of the original code snippet:-
However, I have a lot of files using the SysthemVerilog syntax, and editing each "for" statement in each file into a "generate for" as in the above example is a tedious task.
Is there a way to get Quartus to synthesize the files as they are, in the SystemVerilog syntax of using "for" without an explicit "generate" as above?
Thanks!
Akshay
I am trying to synthesize a SystemVerilog (.sv) file in Quartus Prime Version 16.0.0.
I get the following error while using "for" statements without the explicit "generate" statement: (error) near text: "for"; expecting "endmodule"
The code snippet giving the error is as follows:
Code:
for(genvar i=0; i<4; i=i+1)
always_ff@(posedge clk[i])
o_data[i] <= i_data;I have also included the comment "// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005" at the first line of my .sv file.
As a workaround, I can get Quartus to synthesize my file correctly using the following edited version of the original code snippet:-
Code:
genvar i;
generate for(i=0; i<4; i=i+1) begin : name_1
always_ff@(posedge clk[i])
o_data[i] <= i_data;
end
endgenerateHowever, I have a lot of files using the SysthemVerilog syntax, and editing each "for" statement in each file into a "generate for" as in the above example is a tedious task.
Is there a way to get Quartus to synthesize the files as they are, in the SystemVerilog syntax of using "for" without an explicit "generate" as above?
Thanks!
Akshay