CVI overflow and CVO underflow
Hi, CVI(run control) -- CVO(run control) , cvi always overflow,cvo always underflow. why? How to set the fifo depth? nios config code is as follows, /**************************** CTI...
View ArticlePossible to call verilog code from a c program running on a soft processor on...
I have a soft NIOS II processor instantiated on an Altera FPGA. I have 4 JTAG pins connected from the FPGA to a FTDI chip (lets call them A1, A2, A3, A4). I have the JTAG pins from 2 MCUs connected to...
View Articleissue with avalon streaming witdth convertion
hi, everyone! I am new to FPGA and NIOS I was trying to capture frame from the vip test pattern generator and write to sdram using SGDMA. But the data came from the test pattern generator was 24bit(R G...
View ArticleQsys NCSIM : ncvlog: *E,ERRIPR: error within protected source code
Hi All, Please give your valuable suggestion for this issue, I was trying to simulate one of my Qsys design. Simulation runs successfully when I use ModelSim-Altera. But fails with Cadence. The error...
View ArticleSend data from FPGA to computer using a USB to TTL
Hi, i'm a newbie using FPGAs and i'm trying to send data from FPGA to computer using a USB to TTL adapter but so far the only thing i can send is just one bit, i can see it on putty, is just trash...
View ArticleEthernet to UART Converter NIOS - HAL or MicroC?
Hello all, I've done a fair bit of simple C coding on Microcontrollers (mostly Atmel) and a bunch of VHDL coding, but not much SOC, so I'm a bit new to NIOS. I've implemented a simple UART with a FIFO...
View ArticleSynthesis support for SystemVerilog files in Quartus Prime Version 16.0.0
Hi all, I am trying to synthesize a SystemVerilog (.sv) file in Quartus Prime Version 16.0.0. I get the following error while using "for" statements without the explicit "generate" statement: (error)...
View ArticlefindPlatform() Call Changes Directories
I have a Cyclone V Development Kit. I have compiled my host code to a shared library (.so) and I am using this to make opencl calls from python using ctypes.cdll. Let's say I am running my program from...
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MAX10/DE10-Lite board : SDRAM(64MB) problem downloading elf-file
Hi All, I am using the DE10-Lite board with Quartus version 16.1. My application is running without any problems on a DE1 board (8MB SDRAM), on a DE0-Nano board(16MB SDRAM) and on a BeMicro CV board...
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Error 332000 when using DCFIFOs in Qsys during build
I received this error message in Quartus Prime Lite 16.1 when attempting to add a dual-clock FIFO to Qsys on a DE2i-150 example project. I tested this with the DE2i-150 PCI-E Fundamental example...
View ArticleQuestion about Stratix IV act like disk drive?
I have project that build hardware system on FPGA, it contains module SGDMA, PCIe Avalon MM, DDR3 Controller and HDMI Controller. PC communicate with FPGA through PCIe Link. I used windriver generate...
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How to create BSP
Hi my friends I want to create the BSP for the DE1-SoC kit "http://www.terasic.com/downloads/cd-rom/de1-soc/DE1-SoC_opencl_BSP_16.0.zip", I want how they did it in the photo. I know ".cl" and ".cpp"...
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How to create like BSP
Hi my friends I want to create the BSP for the DE1-SoC kit "http://www.terasic.com/downloads/cd-rom/de1-soc/DE1-SoC_opencl_BSP_16.0.zip", I want how they did it in the photo. I know ".cl" and ".cpp"...
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How to create like BSP
Hi my friends I want to create the BSP for the DE1-SoC kit "http://www.terasic.com/downloads/cd-rom/de1-soc/DE1-SoC_opencl_BSP_16.0.zip", I want how they did it in the photo. I know ".cl" and ".cpp"...
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How to create like BSP
Hi my friends I want to create the BSP for the DE1-SoC kit "http://www.terasic.com/downloads/cd-rom/de1-soc/DE1-SoC_opencl_BSP_16.0.zip", I want how they did it in the photo. I know ".cl" and ".cpp"...
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How to create like BSP
Hi my friends I want to create the BSP for the DE1-SoC kit "http://www.terasic.com/downloads/cd-rom/de1-soc/DE1-SoC_opencl_BSP_16.0.zip", I want how they did it in the photo. I know ".cl" and ".cpp"...
View ArticleMAX10: Failed to download pof file.
I successfuly download sof file but when I try to download a pof file it fales. I create the pof file fom a sof file Convert Programming Files->Programmer Object File(.pof)->Mode(Internal...
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Driving external ADC in Nios II Eclipse
Hi, recently i've been working on a project "digital oscilloscope" using lcd monitor as display via vga port which mainly uses Altera DE1 board, Altera Quartus II, Nios II and Qsys. I'm using MCP3002...
View ArticleTiming Constraints for ADC LVDS DDR
Can somebody recommend a good constrains for Timing Constraints for ADC LVDS DDR ???
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Using FPGA to HPS-Bridge
I am trying to read Data from the FPGA via the FPGA2HPS-Bridge. When trying to read, the HPS freezes. Is there some kind of tutorial or example for an C-Progam that reads the data out of the...
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