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Nios!!! Elf to sof - problem
Hello, I try make sof file with elf according to this youtube manual. https://www.youtube.com/watch?v=joFaxLY-rUE I have problem, during compilation. Please how do I solve? :( Please see jpg picture...
View Articleschematic for MAX10 dev kit
where is the schematic, / pin out diagram for this dev kit, there is NOTHING in the user manual, and nothing came with the kit? :mad:
View ArticleCVI overflow and CVO underflow
Hi, CVI(run control) -- CVO(run control) , cvi always overflow,cvo always underflow. why? How to set the fifo depth? nios config code is as follows, /**************************** CTI...
View ArticlePossible to call verilog code from a c program running on a soft processor on...
I have a soft NIOS II processor instantiated on an Altera FPGA. I have 4 JTAG pins connected from the FPGA to a FTDI chip (lets call them A1, A2, A3, A4). I have the JTAG pins from 2 MCUs connected to...
View Articleissue with avalon streaming witdth convertion
hi, everyone! I am new to FPGA and NIOS I was trying to capture frame from the vip test pattern generator and write to sdram using SGDMA. But the data came from the test pattern generator was 24bit(R G...
View ArticleQsys NCSIM : ncvlog: *E,ERRIPR: error within protected source code
Hi All, Please give your valuable suggestion for this issue, I was trying to simulate one of my Qsys design. Simulation runs successfully when I use ModelSim-Altera. But fails with Cadence. The error...
View ArticleSend data from FPGA to computer using a USB to TTL
Hi, i'm a newbie using FPGAs and i'm trying to send data from FPGA to computer using a USB to TTL adapter but so far the only thing i can send is just one bit, i can see it on putty, is just trash...
View ArticleEthernet to UART Converter NIOS - HAL or MicroC?
Hello all, I've done a fair bit of simple C coding on Microcontrollers (mostly Atmel) and a bunch of VHDL coding, but not much SOC, so I'm a bit new to NIOS. I've implemented a simple UART with a FIFO...
View ArticleSynthesis support for SystemVerilog files in Quartus Prime Version 16.0.0
Hi all, I am trying to synthesize a SystemVerilog (.sv) file in Quartus Prime Version 16.0.0. I get the following error while using "for" statements without the explicit "generate" statement: (error)...
View ArticlefindPlatform() Call Changes Directories
I have a Cyclone V Development Kit. I have compiled my host code to a shared library (.so) and I am using this to make opencl calls from python using ctypes.cdll. Let's say I am running my program from...
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MAX10/DE10-Lite board : SDRAM(64MB) problem downloading elf-file
Hi All, I am using the DE10-Lite board with Quartus version 16.1. My application is running without any problems on a DE1 board (8MB SDRAM), on a DE0-Nano board(16MB SDRAM) and on a BeMicro CV board...
View ArticleUnable to determine the execution envoronment of the Intel FPGA SDK for OpenCL
At a command prompt, invoke the aoc --version command. Example output: aoc: Unable to determine the execution envoronment of the Intel<R> FPGA SDK for OpenCL<TM> aoc: Detailed error:...
View ArticleCan't download University Program Installer (Linux) 15.0
I'm looking for the University Program Installer Linux 15.0, but the download page https://www.altera.com/support/train...p_version=15.0 has been down (the installer for other versions is still...
View Article[Timing Constraints]: Binding asynchronous clock group constraint to module?
Hello, We are designing one block (similar to mega-function which is having some pre-defined logic). That block can be instantiated by end user in his/her design. We are also planning to automate...
View ArticleALTLVDS_TX Not Working Cyclone IV
Hi, I´ve been using a Cyclone IV -E ( EP4CE115F29C7N) and DE2-115 dev kit. I'm trying to use the ALTLVDS_TX IP in my project and since I wasn't getting no output data from it, I decided to test the IP...
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Adding non-addressable memory causes Downloading ELF Process Failed message
I systematically removed components and narrowed my problem to just one: a 64kB 64-bit On-chip ram that is NOT accessed/connected to the Nios II. I developed a subsytem that exclusively uses that...
View ArticleArria 10 Ethernet Connection Issue
Hi everyone, I am having an issue with the ethernet connection dropping on the Arria 10 board after reprogramming the board with a bit file. On start-up I can ping the host computer from Linux running...
View ArticleMissing files in PHYLite IP example design.
I have an instance of the Altera PHYLite IP v16.1, using dynamic reconfiguration. And, after clicking the Generate Example Design... button, I get a readme.txt file, which says this: Quote: Notes: When...
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Nios!!! Elf to sof - problem
Hello, I try make sof file with elf according to this youtube manual. https://www.youtube.com/watch?v=joFaxLY-rUE I have problem, during compilation. Please how do I solve? :( Please see jpg picture...
View Articleschematic for MAX10 dev kit
where is the schematic, / pin out diagram for this dev kit, there is NOTHING in the user manual, and nothing came with the kit? :mad:
View Article