Hello all,
Being a newbie in VHDL, I am sure theres a stupid mistake somewhere. I just can not get my head around it.
There is no output . I am using activehdl as the compiling tool and it gives no error during compilation.
Can someone please help.
thanks alot
i wanna design an AOI_gate that the inputs are 2 std_logic_vectors.like this:
a.jpg
this is my code:
when i write the code like this i have output:
Being a newbie in VHDL, I am sure theres a stupid mistake somewhere. I just can not get my head around it.
There is no output . I am using activehdl as the compiling tool and it gives no error during compilation.
Can someone please help.
thanks alot
i wanna design an AOI_gate that the inputs are 2 std_logic_vectors.like this:
a.jpg
this is my code:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity AOIGATE is
generic(N : natural:=4);
port(
a,b : in std_logic_vector(N-1 downto 0);
z : out std_logic );
end AOIGATE;
architecture structural of AOIGATE is
signal x : std_logic_vector(N-1 downto 0);
signal y : std_logic;
begin
x <= a and b;
process(x)
begin
for i in 0 to N-1 loop
y <= x(i) or y ;
end loop;
z <= not y;
end process;
end structural;Code:
...
architecture structural of AOIGATE is
signal x : std_logic_vector(N-1 downto 0);
signal y : std_logic;
begin
for i in 0 to N-1 loop
x <= a and b;
z <= x(i)or y ;
end loop;
end structural;