Stratix II ES180 board, help me with DAC output
Hi all, I am in trouble with ADC module. I try to code a very simple code: module dac_test( input clk, output [13:0] dac ); assign dac = 14'b11110001010110; endmodule with clk is 1Mhz clock and I...
View ArticlePISO (4 bit parallel in serial out shift reigster)
Hello, I'm trying to create a simple 4-bit parallel in and serial out shift register. So far, here is what I have: Quote: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE...
View ArticleuC/OS-II Help Needed
Dear Engineers. I am working on a project written before using ecos, now I want to run it on NIOS II and I converted the code but I face a problem now, how can we create and deal with Flags. for...
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No Output from my VHDL code !?
Hello all, Being a newbie in VHDL, I am sure theres a stupid mistake somewhere. I just can not get my head around it. There is no output . I am using activehdl as the compiling tool and it gives no...
View ArticleCannot run program "vsim"
Hi, When I try to verify a demo design in DSP Builder, I am getting the following error: "Cannot run program "vsim":....The system cannot find the file specified". But I have set the path of vsim.exe...
View ArticleError: (vcom-11)
Hi, I am trying to get started with DSP Builder and I started with a demo (as per chapter 4 of DSP Builder User Guide). I tried to verify the design by selecting "Verifying at subsystem level" but I am...
View ArticleDQS and DLL
Hello, I am trying to understand how the DLL works to delay the DQS input. From what I understand, the input clock to the DLL must have the same frequency as the DQS signal and hopefully not much of a...
View ArticleIs CONF_DONE read by the FPGA?
Hi All, I'm debugging a board with a Cyclone IV device where the CONF_DONE pin was inadvertently left floating. The FPGA configures fine over JTAG but when configuring from EPCS it reads the whole...
View ArticleModelsim simulation error
Hi I am using Modelsim student edition 10.2 to simulate my project i am getting following error can any one help me in fixing this error # Permission denied. (errno = EACCES) # ** Error: VHDL Compiler...
View Articlevhdl signed multiplication
how to convert the following unsigned 8x8 multiplication program to "signed 8x8 multiplication"...??? library IEEE; use IEEE.std_logic_1164.all; entity vmul8x8p is port ( X: in STD_LOGIC_VECTOR (7...
View Articlealtlvds_rx data ordering
I am using an altlvds_rx mega-function with Arria V. How does the reciever's output data is ordered with respect to the serial input data, MSB/LSB first? meaning, if i use a SERDES factor of 2, and the...
View ArticleNeed help with VHDL error here
Error (10476): VHDL error at scomp.vhd(64): type of identifier "AC_SHIFTED" does not agree with its usage as "std_logic_vector" type Error (10558): VHDL error at scomp.vhd(64): cannot associate formal...
View ArticleModelsim Altera Starter & .tb
Hi , I use modelsim Altera starter 10.1b unlicensed and i can't use testbench file and simulate. My simulation is good when i use "simulate without optimization" and not with "simulate" . I need...
View ArticlePlease help me read audio file from SDRAM !!!???
Hi all, I using media core of altera and it running very well!! And now I want to run audio file from SDRAM, include write data to SDRAM and read it to line out of the board. So, who have some idea can...
View ArticleLAB Optimization
Hi, I've developed an IP Core, were there's a lot of logic operations (xor). All of them are done in a single clock cycle. My IP uses 35.000 LUTs out of 55.000 availalbe in my ARRIA II GX device....
View Articleavalon master SOPC Builder
ello I have a module that contains a verilog file, I need to create a avalon master interface to connect the module to the other modules of the design is that someone can give me the details and the...
View ArticleSVF / STAPL Support for Cyclone V Device 5CGXFC4C6F23I7
Hi, Using a current, full version, paid subscription of Quartus II 64-bit version 12.1 SP1, the capability of generating any programming file for the Cyclone V device 5CGXFC4C6F23I7 does not appear to...
View ArticleError: Cell fed by 5 non-global control signals ...
I get several (189) errors of the same type for my fpga fabric (vhdl modules): Cell <name> fed by 5 non-global control signals -- only 4 control signals may be non-global My problem is that I...
View ArticleHi, How to choose the speed grade in an FPGA or CPLD?
Hi I've a lot of questions about FPGAs and CPLDs speed grade, I want to generate a pulse of 3 ns acording to an event, which means that I need at least a 333 MHz clock, either external or using a PLL,...
View ArticleNeed help writing timequest constraint(s) for multiple registers
Hello, I have one register in my design that I want to treat differently from others. Let's call this reg_A. All of my registers are asynchronous to any input clock, so I'm using set_max_delay. In this...
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