Convert jic file to jam file with command line
I know that I can converta Jic file from the UI but I want to integrate this into our build server by using command line. To convert the Jic to Jam I go to the programmer, add the jic file, Go to menu...
View ArticleVGA Calculator Display using VHDL
All right, so I'm trying to make a floating point calculator using VHDL, and basically, I want to first make the display. I want this calculator to display on a VGA monitor, and before I start...
View Articlealtera_pll megafunction device speed grade values
What do various speed grade values mean in the altera_pll megafunction? I see things such as - 5_H3, 5_H4, 6_H6, etc. Cannot find these in documentation anywhere.
View ArticleConcurrent writes in multi-ported memories
Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, the...
View ArticlePci i/o drive voltage
Anybody please help!! PCI I/O pins in ALTERA STRATIX are specified as 5V tolerant if we activate the clamp diode in the design handbook if . Kindly say whether a 5V logic input can be tied to this pin...
View ArticleProblem with integrating Qsys system in Quartus with created Qsys PWM module
I'm busy with a projects for a month now and I now need to create a PWM component to add it to my main system. After some googling I found a design example with a PWM (pulse-width modulator) to...
View Articleproblem with "commas and word alignement"
hello, i'm student and i'm working on the receiver parts of "SERDES" ,my program is in VHDL. for explain my project, I receive a incoming serial data. In the first time, i use a PRBS for test the...
View ArticleFailure rate needed for EPM240T100I5N
Hi, I was wondering if there was a document that I could look at that would contain either the MTTF/MTBF or FIT data on Altera CLPDs. More specifically I need the data for the following component...
View Articleerror sopc builder
hi i have this error when i add my own component en verilog with an interface avalon Error: rtp_tx_0.ram_master: ddr_sdram.s1 (0x0..0x1ffffff) is outside the master's address range (0x0..0xf) thank you
View ArticleMDIO module
Hello all, I am trying to access registers in a device communicating with my CycloneIV through MDIO clause 22. I added the "Ethernet MDIO" module in my QSys design along with Nios. My question is: how...
View ArticleExternally clocking ALTLVDS with a large number of channels
I'm attempting to fit a 29 channel ALTLVDS clocked by an external PLL into a EP4SGX70HF35C2 Stratix IV. I get the following error from the fitter: "Error (176143): Project contains fast PLL driving 29...
View ArticleFast Input Register Logic Option
Hi, I have a problem while setting fast input register logic option on input data pins. The problem is I can not place register on input since I am synchronizing input data internally using 4 different...
View ArticleHilbert Transform
Hello, was wondering if anyone has implemented a Hilbert Transform on an FPGA? If so, can you share your comments or suggestions? Respectfully, joe
View ArticleProblem to use SDR SDRAM with stratix IV and stratix V FPGA boards
We are working in a project that needs to use a SDR SDRAM. We are using 3 FPGA boards Clyclone DE2, stratix IV, and stratix V. The DE2 board does not support the complete project and even can run in...
View ArticleUnderstanding how tool treats HDL code- Verilog blocking and non-blocking...
Hello, I am learning Verilog and trying to understand how particular code is synthesized later on. I understand that blocking statements has a procedural flow as mentioned bellow (ref: asic-world). 1...
View ArticleClik here to view.
Reducing number of pins to connect SDRAM
Hello, I have a design based on the 144 pin EP3C25. I programmed a NIOS II processor with external SRAM connected to the FPGA but for this I need more than 30-pins. In order to reduce this amount I...
View ArticleGenerating sine wave in Verilog
Hai all, I need to generate a sine wave in verilog.. I have the look up table values .. but i dont know how to get the sine angles form that.. I am scaling it to 1024 samples.. below are some of the...
View ArticleI need help to get a license that allows compile vhdl code
I have downloaded the max plus II software and got a license from altera to use the software.The problem is that when I try to compile a VHDL code appears a message tha the license used doesn't support...
View ArticleLooking For ASIC/FPGA Developer SHA256
Hello, Iam looking for ASIC/FPGA Developer SHA256. Please pm me the contact details including your text or voice chat messenger ID. :) Thanks
View ArticleGPIOLIB Support
Has anyone attempted to enable GPIOLIB support? Trying to enable support for the pcf8575 I2C GPIO expander requires GPIOLIB to be enabled, however, I am getting compilation errors referring to:...
View Article