PCIe transceiver offset cancelation
Device - Stratix IV Using PCIe x4 Gen2. For the purpose of Transceiver offset cancelation I am using the external alt_gx_reconfig. I have been using a PLL output to feed this clock and using the...
View ArticleNest if statement in case statement
Hi, Is it customary and synthesizable to use nested 'case' statement inside the 'if' statement? Tnx
View Articleusage of JTAG-UART without NIOS CPU and avalon interfaces
Dear experts, I have a module, which is connected to 3C120 development kit via HSMC connector. This module exports several UARTs. In order to avoid cluttering the device with cables I'd like to use...
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Enhance Interrupt initiation
Hello Friend's, I am trying to use following code for using Enhance Interrupt Initiation but a am not able to initialize Enhance Interrupt, every time i run the application it return -1, mean interrupt...
View Articlealtlvds_rx data ordering
I am using an altlvds_rx mega-function with Arria V. How does the reciever's output data is ordered with respect to the serial input data, MSB/LSB first? meaning, if i use a SERDES factor of 2, and the...
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Concept of CRC24 calcualtion for 64 bits
Hi, Does anyone knows concept of CRC calculation? (which is generated by ALTERA for Interlaken protocol core ) Kindly refer the document of advanced synthesis cookbook. I don't know how are they doing...
View Articlealtlvds_rx data ordering
I am using an altlvds_rx mega-function with Arria V. How does the reciever's output data is ordered with respect to the serial input data, MSB/LSB first? meaning, if i use a SERDES factor of 2, and the...
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boot configuration files from NOR Flash
hi, i am using a Cyclone IV device,NOR Flash(PC28700BP30EF),JTAG,EPCS ans a external Switch, the arragement is shown in attached figure. i have to flash two different images(A and B) in NOR Flash. i...
View ArticleNios II seems stuck in reset mode, sysid and timestamp not found...
Hi, I am trying to implement a Nios on my custom board. The nios is simple: - external clock 30MHz - external reset_n (alt_pll_locked signal) - nios II processor /s - onchip memory: 131072 bytes -...
View Articlefor module 'cpu' did NOT run successfully.
hello I tried to create a new component with the SOPC Builder, this component is in the form of a verilog file "rtp_tx.v" which must have two interface, avalon master interface to connect with ddr...
View Article[SOPC Builder] pixel treatment in different clock domain
Hello everybody, Actually I am developping a custom core which calculate the GreyScale value of each coming pixel. My system provides 800x600 resolution wich means 40 Mhz pixel clock, while my...
View ArticleQuestions in PCIe BAR
1. Why do we need BAR in PCIe? 2. Why do we need multiple BARs in PCIe? 3. How do we choose type of BAR in PCIe? (64 bits/34 bits, Prefetchable/non-prefetchable) 4. With multiple devices (a RAM, a...
View ArticleStratix V Kit-Programming SiLabs 5338 w/ FPGA
I have the Stratix V GX development kit, that has two SiLabs 5338 devices that can be programmed using the Clock Control GUI and the JTAG programmer. What I want to be able to do is program the Si5338s...
View ArticleModelsim-Altera Simulation Error: Memory Allocation Failure
Hello everyone, I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation. I have...
View ArticleCyclone V with M25P16 configuration device
Will Numonyx M25P16 work with Cyclone V AS configuration? Can I program it through the JTAG port? Will it work with compression? I seem to remember a problem we had in the past where Quartus did not...
View ArticleProgramming .pof file with SFL
Hi, I have a .pof file (periphery image for CvP automatically generated by Quartus) which I'm trying to program into a EPCS128 device with the Quartus Programmer in JTAG mode. I'm trying to use the...
View ArticleUsing HIP PCIe from Cyclone V Development board to communicate to PC
I am trying to implement HIP PCIe in Cyclone V development board to communicate with a PC. In PC I have jungo driver installed. In QSYS, I have instantiated: 1. PCIe_1x4 (Avalon Memory mapped) with one...
View ArticleDoes an FPGA need an external clock source?
Is it mandatory to connect the FPGA clock pins to clock source. I am implementing USART in the fpga which is driven by synch clock and data given to thE I/O pins of FPGA. kindly help??
View Article.sof is not genrated (urgent)
.sof is not generated. We have used megacore FFT function to build in to an IP of Qsys..it is generated without any error. but when we include this IP in our top level .sof and is not generated even if...
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about vhdl code for cic interpolation filter
i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic...
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