How to use Altera BRAM instance as a DualPort RAM with 1 Write and 2 parallel reads

Hi,

I had used altsyncram for writing into first port and reading from the second port in a DUAL_PORT mode. Everything seems to be working in the simulation and in the hardware. Now the design changes demand writing data into PortA, and ability to read simultaneously from PortA and from PortB. I modified the altsyncram configuration to make it BIDIR_DUAL_PORT with the following instance usage


altsyncram #(
.address_aclr_b ("CLEAR0" ),
.intended_device_family ("Stratix V" ),
.lpm_type ("altsyncram" ),
.numwords_a (DATA_DEPTH ),
.numwords_b (DATA_DEPTH ),
.operation_mode ("BIDIR_DUAL_PORT" ), // Single Port Access
.outdata_aclr_b ("CLEAR0" ),
.power_up_uninitialized ("TRUE" ),
.ram_block_type ("M20K" ),
.read_during_write_mode_mixed_ports ("OLD_DATA"),
.widthad_a (ADDR_WIDTH ),
.widthad_b (ADDR_WIDTH ),
.width_a (1 ),
.width_b (1 ),
.width_byteena_a (1 )
)
altsyncm20k_mask
(.aclr0 (1'b0 ),
.address_a (maskindex_ff),
.clock0 (clk ),
.data_a (maskin_ff),
.wren_a (wr_ff),
.address_b (cam_index_ff),
.aclr1 (1'b0 ),
.addressstall_a (1'b0 ),
.addressstall_b (1'b0 ),
.byteena_a (1'b1 ),
.byteena_b (1'b1 ),
.clock1 (clk ),
.clocken0 (1'b1 ),
.clocken1 (1'b1 ),
.clocken2 (1'b1 ),
.clocken3 (1'b1 ),
.data_b (1'b0 ),
.eccstatus ( ),
.q_a (maskstatusoutHost ),
.q_b (maskstatusouttbt),
.rden_a (lookupdirect_ff&~wr_ff),
.rden_b (cam_match_ff&lookuptbt_ff),
.wren_b (1'b0 )
);


Surprisingly the simulation gives valid reads from both the ports, but in hardware the readdata from PortB isnt valid, but readvalue from PortA is correct.

1) What could be the reason why read on PortB fails in hardware. I went through the https://www.altera.com/ja_JP/pdfs/li...ug_ram_rom.pdf, but couldnt make out any mistakes.

2) Whats the difference between altsyncram and altdpram(UseCase) ?.


References: FPGA Used: StratixV
ADDR_WIDTH:11
DATA_DEPTH:2048


Thanks in advance
Jeebu Jacob Thomas