ALTPLL Design Example
Hello everyone I am trying to find an507_altpll_dynphase_de2.zip design example. apparently, it has been removed from Altera website. can someone show me where I can find this design example. the...
View ArticleQuestions about SOC FPGA Preloader and device tree
Hi IÂ’m working on a project using the Terasic Spider robot which uses the DE0 NANO SOC board. It is a Cyclone 5 board. IÂ’m building a Metal Detection application on top of the spider and IÂ’m using the...
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Quartus II Web Edition 13.1.0.162 Installation window not responding
Hello Everyone, This is my first post in this forum. If you happen to find any corrections to be made to this post, please let me know. I recently downloaded the Quartus II Web edition version...
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Progress stops during compilation
I have installed Quartus pro version 17.0, along with Altera OpenCL version 17.0, and I am attempting to compile the example projects (hello_world, vector_add). I have followed as many threads as I...
View ArticleWindows 10 driver support for USB Blaster ?
In reviewing the drivers download page it appears there are NO drivers for Windows 10 for the USB based Blaster programmer cables. Is this really true ?
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Got CL_INVALID_BINARY error when emulated HelloWorld example on Windows
I followed the "aocl_getting_started.pdf" instruction to implement the hello_world example on Window. But I got error message about CL_INVALID_BINARY when I tried to run the emulator. The steps that...
View Articleaddressing in Nios II processor
Hello all, I want to know about dynamic and native addresses and their alignment in Nios II processor. I do not understand how these addresses are used and incremented for addressing any location in...
View ArticleBoard support package of Cyclone V GT Kit for OpenCL for window
Hi I'm trying to get OpneCL working on Cyclone V GT (not Soc). However the OpenCL SDK by Altera doesn't include the board support for Cyclone V GT. I found someone made the support package on...
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88e1111 phy
I have designed Cyclone V FPGA based board. When i try to program, initial configuration is not working in Ethernet PHY. Can't see any LED glowing in Ethernet PHY. Hereby I have attached Ethernet PHY...
View ArticleA question about the toggle in early power estimation (EPE)
Hi I have used the EPE tool based on excel. I cannot determine the value of the toggle. I have some questions about the toggle values. Are the toggle values in the "Logic", "Ram", "DSP", "IO" the same...
View ArticleGPIO Expansion Header pinout for De1-SOC and De10 standard boards
Hello, I'm looking for complete pinot of GPIO Expansion Header for De1-SOC and De10 standard boards. Every header has 40 pins, all data I've found describes only 36 pins of GPIO. Which pins are 5V...
View ArticleHow to use Altera BRAM instance as a DualPort RAM with 1 Write and 2 parallel...
Hi, I had used altsyncram for writing into first port and reading from the second port in a DUAL_PORT mode. Everything seems to be working in the simulation and in the hardware. Now the design changes...
View ArticleError during QSYS generation
I'm getting strange error during generation of system with DDR2 controller Error: GenerateSim: Could not move C:\Users\WAT\AppData\Local\Temp\alt7310_6655338575...
View ArticleError(11999): Channel(s) under reference clocks - arria 10 development kit...
I'm designing a system on an Arria 10 development kit which uses the FMC connectors as I/O, and have assigned pins according to the user guide. The design passes analysis and synthesis, however I...
View ArticleBest practice to define bidirectional pin in top level design file with...
Being new to Quartus II and still in the phase to build some simple tests I used the Pin planner to define a bidirectional pin. This resulted in the following top level design file test1_top.v: Code:...
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Powerplay Result
Hi,I have generated a .vcd file and insert it into the Powerplay Power Analyzer Tool in Quartus II 11.0,and get the result as follow. I think the dynamic power is too small. IS THIS RESULT CORRECT? And...
View ArticleIssue with POS-PHY level 4 megacore
Hi, I'm using quartus 10.1 sp_1 version. I just instantiated POS_PHY level 4 megacore function. After I generate the IP core, It gives following files. 1. *_tx_core.v2. *_tx_modules.v 3....
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DDR3 SDRAM controller with Uni PHY, DMA and external UART(RS232) qsys...
Hi, I am using MAX 10 FPGA development board (package : 10M50DAF484C6GES). I'm planning to test the memory_test (includes memory test, DMA and FLASH) application in NIOS II. I made a qsys design to...
View ArticleMy first FPGA
Y have a problem with simple counter, becouse my FPGA design won't work. Y did everithing as you demonstrate, but when Y try to implement it on board (in autodetect) VTAP10 goes serial and design won't...
View ArticleMax10 Eval Kit User Flash Memory IP
Hey everyone, I've been trying As a sidenote - I have read the MAX10 User Flash Memory guide in its entirety no fewer than 3 times, however, I have almost zero experience in verilog. I'm trying to use...
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