Hi,
How can I constrain output_delay for a parallel bus driven by a LVDS serdes? I'm trying to do something similar to this: https://www.altera.com/support/suppo...ca_ss_out.html but my "create_generated_clock" constraint for the output_clock fails due to incorrect source (I've tried get_nets on the tx_outclock and generating the clock as a data output and using get_pins on the DDIO register output).
The ug_altera_lvds document suggest to analyse I/O timing by looking at the TCCS report, but this number does not take into consideration the target device's setup and hold requirements.
By using twentynm_ddio_out to generate my 216MHz, 16-bit parallel, source-synchronous DDR output interface I am not even close to meet timing on an Arria 10 GX.
Is it possible to use "set_output_delay" to constrain this interface? If not, how can it be constrained?
How can I constrain output_delay for a parallel bus driven by a LVDS serdes? I'm trying to do something similar to this: https://www.altera.com/support/suppo...ca_ss_out.html but my "create_generated_clock" constraint for the output_clock fails due to incorrect source (I've tried get_nets on the tx_outclock and generating the clock as a data output and using get_pins on the DDIO register output).
The ug_altera_lvds document suggest to analyse I/O timing by looking at the TCCS report, but this number does not take into consideration the target device's setup and hold requirements.
By using twentynm_ddio_out to generate my 216MHz, 16-bit parallel, source-synchronous DDR output interface I am not even close to meet timing on an Arria 10 GX.
Is it possible to use "set_output_delay" to constrain this interface? If not, how can it be constrained?