SOF-file works correctly, POF-file does not
I made the simplest of the simplest NIOS II applications: a LED that blinks endlessly. I have a SOF- and POF-file created by Quartus Prime 16.0.0. Programming the SOF-file and running the NIOS II...
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Using Cylcone V HMCPHY DQ pins as high frequency inputs
I am working on a design that uses two 500MSps ADCs with a DDR interface clocked at 250MHz. The ADC supplies the 250MHz clock to clock the signals into the FPGA (source synchronous). I am using the...
View ArticleMultiple Configuration File for Cyclone IV E
Hallo I am using Cyclone IV E (EP4CE22F17C6) with a slightly customized DE0-NANO board. Currently i am using the JTAG to program the FPGA and its volatile. I know that the board has an EEPROM which is...
View ArticleWhy do images uploaded to the forum appear so small?
Any time I post a thread with images, they appear very small and often unreadable. For example, in the following the first two are unreadable and the second two are fine:...
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Simulation error for mod 3 asynchronous in Quartus II
I have used Quartus II 14.1 (64-bit version). I made a mod 3 asynchronous counter as Fig 1. The functional simulation issues the error message as Fig 2. And, the timing simulation result is weird. I...
View ArticlePLL Source Synchronous Mode
Does anybody know which data is used for a clock to synchronize with it when a PLL is set to the source synchronous mode? Many thanks.
View ArticleGetting segmentation fault if Kernelinput gets bigger
Hello , I have following OpenCL-Host Code, this code convolves the inputsignal with the mask int main() { //inits context and program init_opencl(); SoC_convolution(500,500); clReleaseProgram(program);...
View ArticleModelSim Altera edition improvement
Hello all, This is to request an improvement to ModelSim Altera edition. We are glad that the tool now support mixed simulation, thak you. Would it be possible that in the near future the tool also...
View ArticleAltera LVDS SERDES TX timing
Hi, How can I constrain output_delay for a parallel bus driven by a LVDS serdes? I'm trying to do something similar to this: https://www.altera.com/support/suppo...ca_ss_out.html but my...
View ArticleQuartus II version 13 doesn´t generate pof or jam files... What to do?
Hi! I need to program some EPM3032CPLDs. The bdf file was generated by Quartusversion 13, free download. According the warning after compilation, this versiondoesn´tgenerateprogramming files like *.pof...
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Quartus II 64-Bit Programmer Failed To Load SOF Data For JIC File Generation.
Hi, I was trying to follow the 'Data Mover' tutorial on the 'rocketboards' website. In particular, I was trying to add a (time-limited) sof file as an input for the SOF data. However, it looks like the...
View ArticleCan't fit design in Cyclone V GX
Hi everyone, I'm trying to complete the My First FPGA tutorial (https://www.altera.com/content/dam/a...first_fpga.pdf) and everything works perfectly up until compilation, at which point it gives me...
View ArticleTerasic DE10-nano Question - Why does DE0 rbf work on it?
We recently obtained a Terasic DE10-nano development board and installed their Linux Console (kernel 4.5) image on its SD Card, the board booted up as expected. We noticed we could put our old DE0 raw...
View ArticleArria 10 GX Devkit Programming Issue
When a scan jtag chain is performed on the devkit (all dip switches on default) after an image other than the factory build is programmed to the A10, the configuration flash is no longer seen in the...
View ArticleExtreme Performance Drop while using local memory
I have two simple kernels both doing the same thing, but the only difference is on of them reads the data from global memory, and the other first copy data into local memory and then read it from...
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read HPS SDRAM from FPGA thru Avalon MM bus
Hi, I'm learning Cyclone V SoC some months (LOAN pins, GIO pins, etc) and now I can't read HPS SDRAM memory from a VHDL code in FPGA fabric. I see some posts in this forum but only read 0. Please,...
View ArticleBoard Test System of Arria V GX is not pointing Quartus II software
Hi guys, i have just started to learn about hardware. I am using arria V GX and trying to use its Board Test System (BTS), but it always showing an error "could not find required quartus II version in...
View ArticleEMIF toolkit times out on initialize connections
Hi guys I'm using the Arria 10 dev kit to test an RLDRAM3 EMIF. I have succucessfully programmed the device. Burt when I launch the EMIF toolkit , it get stuck at initialize connections step. I've to...
View ArticleDCFIFO : DCFIFO_MIXED_WIDTHS IP Support on Cyclone IV - V
Hello, In the DCFIFO documentation i see that DCFIFO_MIXED_WIDTHS is supported for Arria 10 with several combination of widths of input and output ports. This is also indicated in table 12 on...
View ArticleQuartus Hardware and Software IP Patches
I want to include patched hardware and software versions of Altera IP in a Quartus QSYS project I am responsible for. On the Quartus/QSYS side of things I simply add the IP folders to the QSYS project...
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