Hello,
In the DCFIFO documentation i see that DCFIFO_MIXED_WIDTHS is supported for Arria 10 with several combination of widths of input and output ports.
This is also indicated in table 12 on https://www.altera.com/documentation...462767872.html.
Can I conclude that the function is not supported on other FPGA types than Arria 10 ?
(I tried in on a Cyclone V with a 16 => 8 bit combination. Only 8 of the 16 bits are passed through the FIFO in Modelsim and the test on my DE0-CV shows the same result. I saw no warnings that the function is not supported in the Quartus 7.0 output.)
Best Regards,
Johi.
In the DCFIFO documentation i see that DCFIFO_MIXED_WIDTHS is supported for Arria 10 with several combination of widths of input and output ports.
This is also indicated in table 12 on https://www.altera.com/documentation...462767872.html.
Can I conclude that the function is not supported on other FPGA types than Arria 10 ?
(I tried in on a Cyclone V with a 16 => 8 bit combination. Only 8 of the 16 bits are passed through the FIFO in Modelsim and the test on my DE0-CV shows the same result. I saw no warnings that the function is not supported in the Quartus 7.0 output.)
Best Regards,
Johi.