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Max 10 JTAG Voltage Question
Hello, I am designing a pcb around the 10M50SC (Max 10) 144 pin chip. I am confused about what voltage the JTAG lines should have. I've read that the pull up voltages for TMS and TDI should be 2.5V not...
View ArticleALTERA MAX 10 How to write custom ADC interface verilog code
Hello guys, I am new to FPGA though I have experience with verilog coding. I am working on a Project where I need to use the ADC of Max 10 at 1MSPS to measure an analog signal and send the binary data...
View ArticleALTERA MAX 10 M50D FPGA to PC data transfer options
Hello All, I am fairly new to FPGA programming. I have a MAX 10M50DAF484C6GES For a new project that I am working on I need a speed of around 12Mbps or roughly 2MBps. I have looked into the UART...
View Article[Linux] altera_sopc_pll directories being created in users's home directory
I have the same problem @sandbender had almost three years ago: https://www.alteraforum.com/forum/sh...ad.php?t=46465 I've been having this issue with several Quartus versions (last tested in 16.1) Is...
View Article.rbf image compatability
Hi, Is it possible to program an .rbf file targeted for a Cyclone V 5CSEMA4U23C6N device onto a 5CSEBA6U23I7NDK device? Are there compatibility issues or rules for doing this? A pointer to a document...
View ArticleMAX 10 Development Kit RGB Led
Hi, I am new to altera FPGAs and purchased recently the MAX 10 FPGA Development Kit, embedded with 10M50DAF484C6GES fpga. I am using the dev-board rev C, and looking at the schematics of the dev-board...
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Auto-negotiation failed in MAX 10 FPGA development kit
Hi, I'm using MAX 10 FPGA development kit (10M50DAF484C6GES). I am using the simple server socket example design (downloaded from altera design store) to test the ethernet ports. I changed the IP...
View ArticleNew thread does not appear
I posted question into FPGA, Hardcopy, and CPLD Discussion section, but question appears neither in the list nor in my thread stats. When I try to resubmit website ways that I already submitted the...
View ArticleRemote-update: watchdog timer
Cyclone 3 device. I am implementing remote update, and always get watchdog timer error for user image reconfiguration as a cause (bit 1 of parameter 111b). Questions: - which value of previous reconf...
View ArticleWhy FPGA OpenCL Matrix Multiplication is better than CPU?
Hello Altera Forum Geniuses ~!~! I have a Question! Today I made Matrix Multiplication kernel code. (.cl) it are 3 codes below~ no _simd __kernel void simpleMultiply( __global float* A, __global float*...
View ArticleArria 10 GX FPGA Development Kit board_update_portal PRD project
Hello everyone, I am very new to the Arria 10 board and am trying to run the Board Update Portal Design from: https://www.altera.com/products/boar...0-gx-fpga.html I can see from the code that there is...
View ArticleAccess to Next-Value of Clocked-Value, Without Needin Clocked and Unclocked...
Greeting All: In VHDL, using a clocked_value in a single process, is it possible to access the next clocked_value, without creating another signal 'next_clocked_value' and controlled in another...
View ArticleArria 10 SoC re-use of integrated security mechanisms for own IP
Hi, is there any possibility to connect the integrated security mechanisms to our own IP core? As an example: If the on-chip Temperature sensor exceets a certain value, this signal shall be passed to...
View ArticleProgramming FPGA from HPS using QSPI
Hello, I have a de1-soc I am trying to program the fpga from the qspi connected to the hps At this time I was able to load the preloader, run a bare metal application on the arm, but when I try to load...
View ArticleAltera download website broken?
Hey, I just got my first FPGA, and I was pretty excited to get started with Quartus Lite, and I was quite sad to find that dl.altera.com is having some server issues right now. Does anybody if this is...
View Articlecarry chain delay difference between real test and Timequest analysis result
Hi all, 5CGXFC7D6F31C7N is used to implement a TDC in my design with QII14.0. according to timequest analysis results, the average carry delays of adder in a ALM are 52ps, 46ps, 27ps, 26ps respectively...
View Article[Altera.com page] some links in the webpage are broken
Hi, I think that altera.com webpage is not so helpful to me in searching information for eg. some links are broken. Did anyone have similar experience? I wonder if there is any Altera personnel in this...
View ArticlePin assignement from DE1 to DE nano
I have a VHDL code writen to work on a "DE1 ALTERA" developement board, now I want to run the same code on a "DEO nano" so that I can make a smaller circuit that can fit in my system. the problem is...
View ArticleSoC FPGA Ethernet Performance
Hi, I have application that needs to transfer 1 gigabit/s of data generated by the FPGA over Ethernet. FPGA generated data would be written to HPS's DDR3-memory. The data would be transferred over 1G...
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